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參數(shù)資料
| 型號(hào)： | Z8018520FSC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SMART PERIPHERAL CONTROLLERS |
| 中文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 91/95頁 |
| 文件大?。?/td> | 484K |
| 代理商： | Z8018520FSC |
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91
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
Z80185 PIA AND MISCELLANEOUS REGISTERS
(Continued)
Parallel Ports
The Z80185 has two 8-bit bidirectional ports. Each bit is
individually programmable for input or output. Each port
includes two registers: the Port Direction Control Register
and the Port Data Register. The second port also includes
an Alternate Address that is used with the Bidirectional
Centronics feature.
1
1
1
1
1
1
1
1
PIA 1 Data Direction Register
0 = Output
1 = Input
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
PIA 1 Data Register
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
PIA 2 Data Register
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
PIA 2 Data Register
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
PIA 2 Data Register
7
6
5
4
3
2
1
0
Figure 94. PIA 1 Data Direction Register
(I/O Address %E0)
The data direction register determines which of the PIA16-
10 pins are inputs and outputs. When a bit is set to 1, the
corresponding bit in the PIA 1 Data Register is an input. If
the bit is 0, then the corresponding pin is an output. These
bits must be set appropriately if these pins are used for
CTC inputs and outputs.
Figure 95. PIA 1 Data Register
(I/O Address %E1)
When the processor writes to the PIA 1 Data Register, the
data is stored in the internal buffer. Any bits that are output
are then driven on to the pins.
When the processor reads the PIA 1 Data Register, the
data on the external pins is returned.
Figure 96. PIA 2 Data Direction Register
(I/O Address %E2)
The data direction register determines which of the PIA27-
20 pins are inputs and outputs. When a bit is set to a 1, the
corresponding pin is an input. If the bit is 0, then the
corresponding bit is an output. These settings can be
overridden by the Bidirectional Centronics Controller.
Figure 97. PIA 2 Data Register
(I/O Address %E3)
When the processor writes to the PIA 2 Data Register, the
data is stored in the internal buffer. Any bits that are output
are then driven on to the pins. In certain modes of the
Bidirectional Centronics Controller, an intermediate regis-
ter called the Output Holding Register is activated, and the
transfer of data from the OHR to the pins is under the
control of the controller.
When the processor reads the PIA 2 Data Register, the
data on the external pins is returned. In certain modes of
the Bidirectional Centronics Controller, reading from this
address reads the data stored in the port register from
PIA27-20 under the control of the controller.
Figure 98. PIA 2 Data Alternate Address
(RW) (I/O Address %EE)
Reading and writing this register is exactly the same as
reading and writing address E3 as described above,
except that in certain modes of the Bidirectional Centronics
Controller, writing to this address sets a “ninth bit” in the
opposite sense from writing address E3, and this drives
one of the control outputs with the opposite polarity.
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