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參數(shù)資料
| 型號： | Z8018520FSC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SMART PERIPHERAL CONTROLLERS |
| 中文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 90/95頁 |
| 文件大?。?/td> | 484K |
| 代理商： | Z8018520FSC |
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90
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLERS
DS971850301
Zilog
Watch-Dog Control Registers
Two registers control WDT operations. These are WDT
Master Register (WDTMR; I/O Address F0h) and the WDT
Command Register (WDTCR; I/O Address F1h). WDT
logic has a “double key” structure to prevent accidental
disabling of the WDT.
Enabling the WDT.
The WDT is enabled by reset, and
setting the WDT Enable Bit (WDTMR7) to 1.
Disabling the WDT.
The WDT is disabled by clearing WDT
Enable bit (WDTR7) to 0 followed by writing "B1h” to the
WDT Command Register (WDTCR; I/O Address F1h).
Clearing the WDT.
The WDT can be cleared by writing
“4Eh” into the WDTCR.
Watch-Dog Timer Master Register (WDTMR;I/O ad-
dress F0h).
This register controls the activities of the
Watch-Dog Timer.
Bit D7.
Watch-Dog Timer Enable WDTE). The WDT can be
enabled by setting this bit to 1. To disable WDT, write 0 to
this bit, followed by writing “B1h” to the WDT Command
Register. Upon Power-On Reset, this bit is set to 1 and the
WDT is enabled.
Bit D6-D5.
WDT Periodic field (WDTP). This 2-bit field
determines the desired time period. Upon Power-on reset,
this field sets to "11".
00 - Period is (TcC * 2
16
)
01 - Period is (TcC * 2
18
)
10 - Period is (TcC * 2
20
)
11 - Period is (TcC * 2
22
)
Bit D4.
If this bit is 1 and the WDT times out, the Z80185
drives the /Reset pin Low to reset external logic. If this bit
is 0, a WDT timer only resets the Z80185 internally.
Bit D3-D0.
Reserved.These three bits are reserved and
should always be programmed as 0011. Reading these
bits returns 0011.
1
1
1
1
0
0
1
1
Should be 0011
7
6
5
4
3
2
1
0
Drive /RESET
0 = WDT output only resets 185
1 = Output of WDT is driven
onto /RESET pin
WDT Periodic Field
00 = Period is (TcC X 2*16)
01 = Period is (TcC X 2*18)
10 = Period is (TcC X 2*20)
11 = Period is (TcC X 2*22)
Watch-Dog Timer Enable
0 = Disable
1 = Enable
Figure 92. Watch-Dog Timer Master Register
(I/O Address %F0)
Watch-Dog Timer Command Register
(WDTCR; I/O
Address F1h). This register is Write Only (Figure 93).
Write B1h after clearing WDTE to “0” - Disable WDT
Write 4Eh - Clear WDT
D7
D6
D5
D4
D3
D2
D1
D0
(B1h) - Disable WDT
(After Clearing WDTE)
1
0
0
1
1
0
1
0
0
1
0
1
0
1
1
0
(4Eh) - Clear WDT to zero
WDTCR (Write Only)
Figure 93. Watch-Dog Timer Command Register
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