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12
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLERS
DS971850301
Zilog
AC CHARACTERISTICS
V
= 5V
±
10%, V
= 0V, CL = 50 pF for outputs over
specified temperature range, unless otherwise noted.
Z80185 / Z80195
(20 MHz)
Min
Z80185 / Z80195
(33 MHz)
Min
No.
Symbol Parameter
Max
Max
Units
1
2
3
4
5
6
tcy
tCHW
tCLW
tcf
tcr
tAD
Clock Cycle Time
Clock “H” Pulse Width
Clock “L” Pulse Width
Clock Fall Time
Clock Rise Time
PHI Rising to Address Valid
50
15
15
(DC)
33
10
10
(DC)
ns
ns
ns
ns
ns
ns
10
10
5
5
30
15
7
8
tAS
tMED1
tRDD1
tRDD1
tM1D1
tAH
tMED2
tRDD2
Address Valid to (MREQ Falling or IORQ Falling)
PHI Falling to MREQ Falling Delay
PHI Falling to RD Falling Delay (IOC=1)
PHI Rising to RD Falling Delay (IOC=0)
PHI Rising to M1 Falling Delay
Address Hold Time from (MREQ, IOREQ, RD, WR)
PHI Falling to MREQ Rising Delay
PHI Falling to RD Rising Delay
5
5
ns
ns
ns
ns
ns
ns
ns
ns
25
25
25
35
15
15
15
15
9a
9b
10
11
12
13
5
5
25
25
15
15
14
15
16
17
18
19
20
tM1D2
tDRS
tDRH
tSTD1
tSTD2
tWS
tWH
PHI Rising to M1 Rising Delay
Data Read Setup Time
Data Read Hold Time
PHI Falling to ST Falling Delay
PHI Falling to ST Rising Delay
WAIT Setup Time to PHI Falling
WAIT Hold Time from PHI Falling
40
15
ns
ns
ns
ns
ns
ns
ns
10
0
5
0
30
30
15
15
15
10
10
5
21
22
23
24
25
26
26a
27
tWDZ
tWRD1
tWDD
tWDS
tWRD2
tWRP
tWRP
WDH
PHI Rising to Data Float Display
PHI Rising to WR Falling Delay
PHI Rising to Write Data Delay Time
Write Data Setup Time to WR Falling
PHI Falling to WR Rising Delay
Write Pulse Width (Memory Write Cycle)
Write Pulse Width (I/O Write Cycle)
Write Data Hold Time From (WR Rising)
35
25
25
20
15
15
ns
ns
ns
ns
ns
ns
ns
ns
10
10
25
15
75
130
10
45
70
5
Notes:
Specifications 1 through 5 refer to an external clock input on EXTAL, and
provisionally to PHI clock output. When a quartz crystal is used with the
on-chip oscillator, a lower maximum frequency than that implied by spec.
#1 may apply.