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參數(shù)資料
| 型號： | Z8018520FSC |
| 廠商： | ZILOG INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SMART PERIPHERAL CONTROLLERS |
| 中文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 83/95頁 |
| 文件大?。?/td> | 484K |
| 代理商： | Z8018520FSC |
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83
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
Z80185 PIA AND MISCELLANEOUS REGISTERS
(Continued)
RAM And ROM Registers
Three registers, ROMBR, RAMLBR and RAMUBR, and two
pins, /ROMCS and /RAMCS, assist with decoding of ROM
and RAM blocks of memory.
1
1
1
1
1
1
1
1
A19-A12 RAMUBR
RAMUBR (I/O Address %EA)
7
6
5
4
3
2
1
0
/ROMCS can be forced to a “1” (inactive state) by setting
bit 5 in the System Configuration Register, to allow the user
to overlay the RAM area over the ROM area.
Figure 83. RAMUBR
(I/O Address %EA)
1
1
1
1
1
1
1
1
A19-A12 RAMLBR
RAMLBR (I/O Address %EB)
7
6
5
4
3
2
1
0
Figure 84. RAMLBR
(I/O Address %EB)
The names RAMUBR and RAMLBR stand for RAM Upper
Boundary Range and RAM Lower Boundary Range. These
two registers specify the address range for the /RAMCS
signal. When accessed, memory addresses are less than,
or equal, to the value in the RAMUBR, and greater than, or
equal to, the value programmed in the RAMLBR, /RAMCS
is asserted.
ROMBR ROM Address Boundary Register
This register specifies the address range for the /ROMCS
signal. When an accessed memory address is less than, or
equal to, the value programmed in this register, but greater
than the size of on-chip ROM (if on-chip ROM is enabled),
the /ROMCS signal is asserted.
1
1
1
1
1
1
1
1
A19-A12 ROMBR
ROMBR (I/O Address %EC)
7
6
5
4
3
2
1
0
Figure 85. ROMBR
(I/O Address %EC)
/RAMCS and /ROMCS are active for accesses by an
external master, as well as by the Z80185 processor. If
/ROMCS and /RAMCS are programmed to overlap,
/ROMCS is asserted and /RAMCS is inactive for addresses
in the overlapping region.
Chip Select signals are active for the address range:
/ROMCS: (ROMBR) >= A19-A12 >=
Size of On-Chip ROM (if enabled, else 0)
/RAMCS: (RAMUBR) >= A19-A12 >= (RAMLBR)
All three of the above registers are set to “FFh” at Power-
On Reset. This means that if on-chip ROM is enabled,
/ROMCS is asserted for all addresses above the size of on-
chip ROM, if not, /ROMCS is asserted for all addresses.
Since /ROMCS takes priority over /RAMCS, the latter will
never be asserted until the value in the ROMBR and
RAMLBR registers are re-initialized to lower values.
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