REV. 1.0.1 V1 LOCKDET O CMOS Lock Detect Output Pin - Clock and Data Recovery PLL B" />
參數(shù)資料
型號： XRT94L31IB
廠商： Exar Corporation
文件頁數(shù)： 42/133頁
文件大小： 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
16
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
V1
LOCKDET
O
CMOS
Lock Detect Output Pin - Clock and Data Recovery PLL Block
This output pin indicates whether or not the Clock and data recovery PLL
block has obtained lock to incoming STS-3/STM-1 signal.
As the Receive STS-3/STM-1 PECL Interface block receives this STS-3/
STM-1 signal, the CDR (Clock and Data Recovery) PLL will attempt to
lock onto this STS-3/STM-1 PECL signal. The Receive STS-3/STM-1
PECL Interface block will (internally) derive a 19.44MHz clock signal
from this incoming STS-3/STM-1 PECL signal. The CDR PLL will then
continuously compare the frequency of this 19.44MHz clock signal, with
that derived from either the Clock Synthesizer block (or from the
19.44MHz clock signal applied to the REFTTL input pin).
If the CDR PLL determines that the frequency difference between these
two signals is less than 0.05%, then it will declare that the CDR PLL is in
Lock. If the CDR PLL determines that the frequency difference between
these two signals is greater than 0.05%, then it will declare the the CDR
PLL is Out of Lock.
0 - Indicates that the CDR PLL (within the Receive STS-3/STM-1 PECL
Interface Block) is declaring the Lock Condition.
1 - Indicates that the CDR PLL is declaring the Out of Lock Condition.
STS-3/STM-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION
E1
TXA_CLK
O
CMOS
Transmit STS-3/STM-1 Telecom Bus Interface - Clock Output Sig-
nal:
This output clock signal functions as the clock source for the Transmit
STS-3/STM-1 Telecom Bus Interface. All signals, that are output via the
Transmit STS-3/STM-1 Telecom Bus Interface (e.g., TXA_C1J1,
TXA_ALARM, TXA_DP, TXA_PL and TXA_D[7:0]) are updated upon the
rising edge of this clock signal.
This clock signal operates at 19.44MHz and is derived from the Clock
Synthesizer block.
F2
TXA_C1J1whether or
not the
O
CMOS
Transmit STS-3/STM-1 Telecom Bus Interface - C1/J1 Byte Phase
Indicator Output Signal:
This output pin pulses "High" under the following two conditions;
Coincident to whenever the C1/J0 byte (of the outbound STS-3/STM-1
signal) is being output via the TxA_D[7:0] output, and
Coincident to whenever the J1 byte(s) (of the outbound STS-3/STS-
3c/STM-1 signal) is being output via the TxA_D[7:0] output.
NOTES:
1. The Transmit STS-3/STM-1 Telecom Bus Interface will indicate
that it is currently transmitting the C1 byte (via the TXA_D[7:0]
output pins), by pulsing this output pin "High" (for one period of
TXA_CLK) and keeping the TXA_PL output pin pulled "Low".
2. The Transmit STS-3/STM-1 Telecom Bus will indicate that it is
currently transmitting the J1 byte (via the TXA_D[7:0] output
pins), by pulsing this output pin "High" (for one period of
TXA_CLK) while the TXA_PL output pin is pulled "High".
3. This output pin is only active if the Transmit STS-3/STM-1
Telecom Bus Interface block is enabled and is configured to
operate in the Re-Phase OFF Mode.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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