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XRT94L31
98
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
NOTE: Test Conditions: TA = 25°C, VCC = 3.3V±5% and 2.5V±5%, unless otherwise specified.
1.2.2
MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS MOTOROLA (68K) MODE
NOTE: The values for t0 through t7 can be found in
TABLE 3: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE, WHEN CONFIGURED TO OPERATE IN THE
INTEL ASYNCHRONOUS MODE
TIMING
DESCRIPTION
MIN.
TYP.
MAX.
UNITS
t0
Address setup time to pALE low
4
-
ns
t1
Address hold time from pALE low
4
-
ns
t2
pRD_L, pWR_L pulse width
320
-
ns
t3
Data setup time to pWR_L low
0
-
ns
t4
Data hold time from pWR_L high
0
-
ns
t5
pALE low to pRD_L, pWR_L low
5
-
ns
t6
Data invalid from pRD_L high
4
-
ns
t7
Data valid from pRDY_L low
-
0
ns
t8
pRDY inactive from pRD_L inactive
3
9
ns
FIGURE 4. ASYNCHRONOUS MODE 2 - MOTOROLA (68K) PROGRAMMED I/O TIMING (WRITE CYCLE)
Address
Data
t
0
CS
ALE_AS
A[6:0]
D[7:0]
RD_DS
WR_R/W
RDY_DTACK
t
2
t
3
t
4
t
1