參數(shù)資料
型號: XRT86VL38_1
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 51/66頁
文件大?。?/td> 425K
代理商: XRT86VL38_1
XRT86VL38
48
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
ACK0
ACK1
Y23
Y24
W22
V21
I
-
DMA Cycle Acknowledge Input—DMA Controller 0
(Write):
The external DMA Controller will assert this input pin “Low”
when the following two conditions are met:
1.
After the DMA Controller, within the Framer has
asserted (toggled “Low”), the Req_0 output signal.
2.
When the external DMA Controller is ready to
transfer data from external memory to the selected
Transmit HDLC buffer.
At this point, the DMA transfer between the external mem-
ory and the selected Transmit HDLC buffer may begin.
After completion of the DMA cycle, the external DMA Con-
troller will negate this input pin after the DMA Controller
within the Framer has negated the Req_0 output pin. The
external DMA Controller must do this in order to acknowl-
edge the end of the DMA cycle.
DMA Cycle Acknowledge Input—DMA Controller 1
(Read):
The external DMA Controller asserts this input pin “Low”
when the following two conditions are met:
1.
After the DMA Controller, within the Framer has
asserted (toggled "Low"), the Req_1 output signal.
2.
When the external DMA Controller is ready to
transfer data from the selected Receive HDLC buffer
to external memory.
At this point, the DMA transfer between the selected
Receive HDLC buffer and the external memory may begin.
After completion of the DMA cycle, the external DMA Con-
troller will negate this input pin after the DMA Controller
within the Framer has negated the Req_1 output pin. The
external DMA Controller will do this in order to acknowl-
edge the end of the DMA cycle.
N
OTE
:
This pin is internally pulled “High” with a 50k
Ω
resistor.
MICROPROCESSOR INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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