參數(shù)資料
型號： XRT86VL38_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 34/66頁
文件大?。?/td> 425K
代理商： XRT86VL38_1
XRT86VL38
31
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
RxCHN0_1/
RxFrTD0
RxCHN1_1/
RxFrTD1
RxCHN2_1/
RxFrTD2
RxCHN13_1/
RxFrTD3
RxCHN4_1/
RxFrTD4
RxCHN5_1/
RxFrTD5
RxCHN6_1/
RxFrTD6
RxCHN7_1/
RxFrTD7
E9
E14
B22
H26
AE25
AF18
AB13
AC7
C9
C13
C19
G21
AA21
AB16
V12
W8
O
8
Receive Time Slot Octet Identifier Output Bit 1
(RxCHNn_1) / Receive Serial Fractional Output
(RxFrTDn):
The exact function of these pins depends on whether or
not the receive framer enables the receive fractional/sig-
naling interface, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_1:
These output pins (RxCHNn_4 through RxCHNn_0)
reflect the five-bit binary value of the current time slot
being output by the receive serial interface. System
equipment can use the RxCHCLKn to sample the five out-
put pins of each channel to identify the time slot being out-
put on these pins. RxCHNn_1 indicates Bit 1 of the time
slot channel being output.
If receive fractional/signaling interface is enabled -
RxFrTDn:
These pins are used as the fractional data output pins to
output fractional DS1/E1 payload data within an inbound
DS1/E1 frame. In this mode, system equipment can use
either RxCHCLK or RxSERCLK to clock out fractional
DS1/E1 payload data depending on the framer configura-
tion.
N
OTE
:
Receive Fractional/Signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from register 0xn122 to ‘1’.
RxCHN0_2/
RxCHN0
RxCHN1_2/
RxCHN1
RxCHN2_2/
RxCHN2
RxCHN3_2/
RxCHN3
RxCHN4_2/
RxCHN4
RxCHN5_2/
RxCHN5
RxCHN6_2/
RxCHN6
RxCHN7_2/
RxCHN7
C9
A15
C22
J23
AF26
AB17
AF12
AF4
D10
D13
F17
J19
W18
AB15
AB9
Y4
O
8
Receive Time Slot Octet Identifier Output-Bit 2
(RxCHNn_2) / Receive Time Slot Identifier Serial Out-
put (RxCHNn):
The exact function of these pins depends on whether or
not the receive framer enables the receive fractional/sig-
naling interface, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_2:
These output pins (RxCHNn_4 through RxCHNn_0)
reflect the five-bit binary value of the current time slot
being output by the receive serial interface. System
equipment can use the RxCHCLKn to sample the five out-
put pins of each channel to identify the time slot being out-
put on these pins. RxCHNn_2 indicates Bit 2 of the time
slot channel being output.
If receive fractional/signaling interface is enabled -
RxCHNn
These pins serially output the five-bit binary value of the
time slot being output by the receive serial interface.
N
OTE
:
Receive Fractional/Signaling interface can be
enabled by programming to bit 4 - RxFr1544/
RxFr2048 bit from register 0xn122 to ‘1’.
RECEIVE SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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