參數(shù)資料
型號： XRT86VL38_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 29/66頁
文件大小： 425K
代理商： XRT86VL38_1
XRT86VL38
26
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
RxSYNC0/
RxNEG0
RxSYNC1/
RxNEG1
RxSYNC2/
RxNEG2
RxSYNC3/
RxNEG3
RxSYNC4/
RxNEG4
RxSYNC5/
RxNEG5
RxSYNC6/
RxNEG6
RxSYNC7/
RxNEG7
D9
D15
D19
G23
AE26
AF19
AB11
AC6
A8
E16
A18
D22
Y20
Y15
AA6
Y3
I/O
12
Receive Single Frame Sync Pulse (RxSYNCn):
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) -
RxSYNCn:
These RxSYNCn pins are used to indicate the single
frame boundary within an inbound T1/E1 frame. In both
DS1 or E1 mode, the single frame boundary repeats
every 125 microseconds (8kHz).
In DS1/E1 base rate, RxSYNCn can be configured as
either input or output depending on the slip buffer configu-
ration as described below.
When RxSYNCn is configured as an Input
:
Users must provide a signal which must pulse "High" for
one period of RxSERCLK and repeats every 125
μ
S. The
receive serial Interface will output the first bit of an
inbound DS1/E1 frame during the provided RxSYNC
pulse.
N
OTE
:
It is imperative that the RxSYNC input signal be
synchronized with the RxSERCLK input signal.
When RxSYNCn is configured as an Output:
The receive T1/E1 framer will output a signal which
pulses "High" for one period of RxSERCLK during the first
bit of an inbound DS1/E1 frame.
DS1/E1 High-Speed Backplane Modes* - RxSYNCn as
INPUT ONLY:
In this mode, RxSYNCn must be an input regardless of
the slip buffer configuration. In 2.048MVIP/4.096/
8.192MHz high-speed modes, RxSYNCn pins must be
pulsed ’High’ for one period of RxSERCLK during the first
bit of the inbound T1/E1 frame. In HMVIP mode,
RxSYNCn must be pulsed ’High’ for 4 clock cycles of the
RxSERCLK signal in the position of the first two and the
last two bits of a multiplexed frame. In H.100 mode,
RxSYNCn must be pulsed ’High’ for 2 clock cycles of the
RxSERCLK signal in the position of the first and the last
bit of a multiplexed frame.
DS1 or E1 Framer Bypass Mode - RxNEGn
In this mode, RxSYNCn is used as the Receive negative
digital output pin (RxNEG) from the LIU.
N
OTE
:
*High-speed backplane modes include (For T1/
E1)
2.048MVIP,
16.384MHz
HMVIP,
modes, and (For T1 only) 12.352MHz Bit-
multiplexed mode.
N
OTE
:
In DS1 high-speed modes, the DS-0 data is
mapped into an E1 frame by ignoring every fourth
time slot (don’t care).
N
OTE
:
These 8 pins are internally pulled “Low” for each
channel.
4.096MHz,
H.100,
8.192MHz,
Bit-multiplexed
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