參數(shù)資料
型號： XRT86VL38_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 21/66頁
文件大?。?/td> 425K
代理商： XRT86VL38_1
XRT86VL38
18
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TxMSYNC0/
TxINCLK0
TxMSYNC1/
TxINCLK1
TxMSYNC2/
TxINCLK2
TxMSYNC3/
TxINCLK3
TxMSYNC4/
TxINCLK4
TxMSYNC5/
TxINCLK5
TxMSYNC6/
TxINCLK6
TxMSYNC7/
TxINCLK7
B10
A17
C24
L24
AC21
AD16
AC8
AF2
A9
B15
E18
K20
U17
AB14
AB3
W5
I/O
12
Multiframe Sync Pulse (TxMSYNCn) / Transmit Input
Clock (TxINCLKn)
The exact function of these pins depends on the mode of
operation selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxM-
SYNCn
In this mode, these pins are used to indicate the multi-frame
boundary within an outbound DS1/E1 frame.
In DS1 ESF mode, TxMSYNCn repeats every 3ms.
In DS1 SF mode, TxMSYNCn repeats every 1.5ms.
In E1 mode, TxMSYNCn repeats every 2ms.
If TxMSYNCn is configured as an input, TxMSYNCn must
pulse "High" for one period of TxSERCLK during the first bit of
an outbound DS1/E1 multi-frame. It is imperative that the
TxMSYNC input signal be synchronized with the TxSERCLK
input signal.
If TxMSYNCn is configured as an output, the transmit section
of the T1/E1 framer will output and pulse TxMSYNC "High" for
one period of TxSERCLK during the first bit of an outbound
DS1/E1 frame.
DS1/E1 High-Speed Backplane Modes* - (TxINCLKn as
INPUT ONLY)
In this mode, this pin must be used as the high-speed input
clock pin (TxINCLKn) for the backplane interface to latch in
high-speed or multiplexed data on the TxSERn pin. The fre-
quency of TxINCLK is presented in the table below.
N
OTES
:
1.
*High-speed backplane modes include (For T1/E1)
2.048MVIP,
4.096MHz,
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
These 8 pins are internally pulled “Low” for each
channel.
8.192MHz,
16.384MHz
2.
3.
TRANSMIT SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
O
PERATION
M
ODE
F
REQUENCY
OF
T
X
INCLK(MH
Z
)
2.048MVIP non-multiplexed
2.048
4.096MHz non-multiplexed
4.096
8.192MHz non-multiplexed
8.192
12.352MHz Bit-multiplexed
(DS1 ONLY)
12.352
16.384MHz Bit-multiplexed
16.384
16.384 HMVIP Byte-multiplexed
16.384
16.384 H.100 Byte-multiplexed
16.384
相關(guān)PDF資料
PDF描述
XRT86VL3x Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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