參數(shù)資料
型號(hào): XRT86VL38_1
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 47/66頁(yè)
文件大?。?/td> 425K
代理商: XRT86VL38_1
XRT86VL38
44
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RDY
V24
R19
O
12
(Con’t)
Power PC 403 Mode - RDY Ready Output:
This output pin will function as the “active-high” READY
output.
During a READ or WRITE cycle, the Microprocessor Inter-
face block will toggle this output pin to the logic high level,
ONLY when the Microprocessor Interface is ready to com-
plete or terminate the current READ or WRITE cycle. Once
the Microprocessor has sampled this signal being at the
logic “high” level upon the rising edge of PCLK, then it is
now safe for it to move on and execute the next READ or
WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor
Interface block is holding this output pin at a logic “l(fā)ow”
level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it samples this output pin
being at the logic low level.
N
OTE
:
The Microprocessor Interface will update the state
of this output pin upon the rising edge of PCLK.
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
V25
V26
U22
U23
U24
U25
U26
T22
T24
R23
R24
P22
P25
N23
N22
P18
N17
T21
T22
R20
R21
R22
P19
P20
N19
N20
M18
M19
L18
L22
I
-
Microprocessor Interface Address Bus Input
These pins permit the Microprocessor to identify on-chip
registers and Buffer/Memory locations within the
XRT86VL38 device whenever it performs READ and
WRITE operations with the XRT86VL38 device.
N
OTE
:
These pins are internally pulled “Low” with a 50k
Ω
resistor, except ADDR[8:14].
DBEN
V23
U22
I
-
Data Bus Enable Input pin.
This active-low input pin permits the user to either enable
or tri-state the Bi-Directional Data Bus pins (D[7:0]), as
described below.
Setting this input pin “l(fā)ow” enables the Bi-directional
Data bus.
Setting this input pin “high” tri-states the Bi-directional
Data Bus.
MICROPROCESSOR INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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