TABLE
參數資料
型號: XRT86VL30IV80-F
廠商: Exar Corporation
文件頁數: 32/175頁
文件大小: 0K
描述: IC FRAMR/LIU T1/E1/J1 QD 80LQFP
標準包裝: 90
控制器類型: T1/E1/J1 調幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應商設備封裝: 80-LQFP(12x12)
包裝: 托盤
其它名稱: 1016-1486
XRT86VL30IV80-F-ND
XRT86VL30
122
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 106: EXCESSIVE ZERO STATUS REGISTER (EXZSR)
HEX ADDRESS: 0X0B0E
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-1
Reserved
-
Reserved
0
EXZ_STATUS
RUR/
WC
0
Change in Excessive Zero Condition Interrupt Status
This Reset-Upon-Read bit field indicates whether or not the “Change in
Excessive Zero Condition” interrupt within the T1 Receive Framer Block
has occurred since the last read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will gener-
ate an interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block detects the Excessive
Zero Condition.
2. Whenever the Receive T1 Framer block clears the Excessive Zero
Condition
0 = Indicates the “Change in Excessive Zero Condition” interrupt has
NOT occurred since the last read of this register
1 = Indicates the “Change in Excessive Zero Condition” interrupt has
occurred since the last read of this register
TABLE 107: EXCESSIVE ZERO ENABLE REGISTER (EXZER)
HEX ADDRESS: 0X0B0F
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-1
-
Reserved
0
EXZ_ENB
R/W
0
Change in Excessive Zero Condition Interrupt Enable
This bit enables or disables the “Change in Excessive Zero Condi-
tion” interrupt within the T1 Receive Framer.
If this interrupt is enabled, then the Receive T1 Framer block will
generate an interrupt in response to either one of the following
conditions.
1. Whenever the Receive T1 Framer block detects the
Excessive Zero Condition.
2. Whenever the Receive T1 Framer block clears the Excessive
Zero Condition
0 - Disables the “Change in Excessive Zero Condition” interrupt
within the Receive T1 Framer Block
1 - Enables the “Change in Excessive Zero Condition” interrupt
within the Receive T1 Framer Block
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