參數(shù)資料
型號(hào)： XRT82L24AIV-F
廠商： Exar Corporation
文件頁數(shù)： 9/39頁
文件大?。?/td> 0K
描述： IC LIU E1 QAUD 100TQFP
標(biāo)準(zhǔn)包裝： 90
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： E1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
其它名稱： XRT82L24AIV-F-ND
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
15
RxClk Clock Sampling Edge
The sampling edge of the RxClk output can be
changed through control bit RClkE within the inter-
face register for receive output data re-timing. With
RClkE=”1”, (Bit 5 = “1”), data is validated on the rising
edge of RxClk and with RClkE=”0”, (Bit 5 = “0”),, re-
ceive data is validated on the falling edge of RxClk. In
Hardware Mode, the state of pin 7 (ClkE) controls the
rising or falling edge of RxClk for data re-timing.
TRANSMIT CLOCK SAMPLING EDGE
NRZ Transmit data at TxPOS/TDATA or TxNEG is
clocked serially into the device using TxClk. With the
interface register bit 4 (TClkE=”1”), input data is sam-
pled on the rising edge of TxClk. The sampling edge
is inverted when TClkE= “0”. In Hardware Mode, the
state of pin 7 (ClkE) controls the sampling edge of
both TxClk and RxClk.
SINGLE RAIL, DUAL RAIL
Transmit data format can be in dual-rail (SR/DR=1) or
single-rail modes (SR/DR=0). In Hardware Mode, du-
al or single-rail format is determined by the state of
pin 8. For single-rail mode operation, NRZ data can
be applied to TxPOS/TDATA with TxClk, while Tx-
NEG input is left unconnected. The transmitter con-
verts NRZ input data into differential signal for trans-
mission to the line using low impedance output driv-
ers.
TRANSMIT ALL ONES (TAOS)
In the Host Mode, individual channels can be pro-
grammed to transmit an all “Ones” AMI signal by set-
ting the per channel bit control TAOS=1. In this mode,
input data at TxPOS/TDATA and TxNEG are ignored.
In Host Mode, reference clock for TAOS is TxClk. If
TxClk is not available, MCLK is used for transmis-
sion. In Hardware Mode, if TxClk is not present and
High for more than 10s, TAOS is transmitted using
MCLK as a reference. Remote Loop-Back has priori-
ty over TAOS request.
HDB3/AMI ENCODER
The encoder is only available in single-rail mode (SR/
DR=1) in Host Mode, or pin 8 set High in Hardware
Mode. In an E1 system, if interface register
CODES=0, HDB3 encoding is selected. Input data
applied to TxPOS/TDATA which contains more than
four consecutive zeros will be removed and replaced
by “000V” or “B00V”, where "B” indicates a pulse con-
forming with bipolar rule and "V" represents a pulse
violating the rule. With register CODES=”1”, AMI
coding is selected. In Hardware Mode, HDB3 or AMI
coding selection is determined by the state of pin 10.
FIGURE 10. DATA CHANGES ON RISING EDGE OF CLK AND DATA IS SAMPLED ON FALLING EDGE
Data Sampled
Clk
Data
Data Sampled
FIGURE 11. DATA CHANGES ON FALLING EDGE OF CLK AND IS SAMPLED ON RISING EDGE
Data Sampled
Clk
Data
Data Sampled
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