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參數(shù)資料
| 型號： | XRT73LC03AIV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 46/61頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| 標準包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-LQFP（14x20） |
| 包裝： | 托盤 |
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XRT73LC03A
48
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.4
b. Operating in the Hardware Mode
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, set the LLB_(n) input pin “High"
and the RLB_(n) input pin "Low".
4.2
THE DIGITAL LOCAL LOOP-BACK MODE.
When a given channel is configured to operate in the
Digital Local Loop-Back Mode, the channel ignores
any signals that are input to the RTIP and RRing in-
put pins. The Transmitting Terminal Equipment trans-
mits clock and data into the XRT73LC03A via the TP-
Data, TNData and TxClk input pins. This data is pro-
cessed through the Transmit Clock Duty Cycle Adjust
PLL and the HDB3/B3ZS Encoder block. At this
point, this data is looped back to the HDB3/B3ZS De-
coder block. After this post-Loop-Back data has been
processed through the HDB3/B3ZS Decoder block, it
outputs to the Near-End Receiving Terminal Equip-
ment via the RPOS, RNEG and RxClk output pins.
Figure 34 illustrates the path that the data takes when
the chip is configured to operate in the Digital Local
Loop-Back Mode.
Configure a channel to operate in the Digital Local
Loop-Back Mode by employing either one of the fol-
lowing two-steps:
a. Operating in the Host Mode
To configure Channel (n) to operate in the Digital Lo-
cal Loop-Back Mode, write a "1" into both the LLB
and RLB bit-fields within Command Register CR4-(n).
b. Operating in the Hardware Mode.
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
XSTS-1/DS3_(n)
E3_(n)
LLB_(n) RLB_(n)
XX
X
1
0
FIGURE 34. THE DIGITAL LOCAL LOOP-BACK PATH WITHIN A GIVEN CHANNEL
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV(_n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData(_n)
TNData_(n)
TxClk_(n)
Notes: 1. (n) = 0, 1 or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in
Hardware Mode.
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing(_n)
Transmit
Logic
Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Digital Local
Loop-Back Path
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
XSTS-1/DS3_(n)
E3_(n)
LLB_(n) RLB_(n)
XX
X
1
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