參數(shù)資料
型號(hào): XRT73LC03AIV-F
廠商: Exar Corporation
文件頁(yè)數(shù): 20/61頁(yè)
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 3CH 120LQFP
標(biāo)準(zhǔn)包裝: 72
類(lèi)型: 線(xiàn)路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 3/3
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-LQFP(14x20)
包裝: 托盤(pán)
XRT73LC03A
25
REV. 1.0.4
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
redundancy to quickly switch out a defective line card
and switch-in the back-up line card.
1.0
SELECTING THE DATA RATE
Each channel within the XRT73LC03A can be config-
ured to support the E3 (34.368 Mbps), DS3 (44.736
Mbps) or the SONET STS-1 (51.84 Mbps) rates. Fur-
ther, each channel can be configured to operate in a
mode/data rate that is independent of the other chan-
nels.
Two methods are available to select the data rate for
each channel of the XRT73LC03A.
1.1
CONFIGURING CHANNEL(n)
For the following disscussion the reader should refer
toTable 2 to determine the appropriate Address for
each command register of each channel in the
XRT73LC03A. The command register description re-
fers to CR(x)-(n), where (x) = 0 to 7 and (n) refers to a
particular channel of the XRT73LC03A.
FIGURE 13. FUNCTIONAL BLOCK DIAGRAM OF THE XRT73LC03A
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF_(n)
Channel 2 - (n) = 2
AGC/
Equalizer
Serial
Processor
Interface
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
Channel 0 - (n) = 0
Channel 1 - (n) = 1
Notes: 1. (n) = 0, 1, or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode.
Device
Monitor
MTIP_(n)
MRing_(n)
DMO_(n)
Transmit
Logic
Duty Cycle Adjust
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
E3_(n)
STS-1/DS3_(n)
Host/(HW)
RLOL_(n) EXClk_(n)
RxOFF
RxClkINV
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
Tx
Control
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