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參數(shù)資料
| 型號(hào)： | XRT73LC00AIV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | E3/DS3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, TQFP-44 |
| 文件頁數(shù)： | 49/53頁 |
| 文件大?。?/td> | 376K |
| 代理商： | XRT73LC00AIV |
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Bit D2 - ALOSDIS (Analog LOS Disable)
This Read/Write bit-field is used to disable the Analog
LOS Detector.
Writing a “0” to this bit-field enables the Analog LOS
Detector. Writing a “1” to this bit-field disables the
Analog LOS Detector.
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.0.0
46
5.1.3
Bit D4 - Reserved
This bit-field has no defined functionality
Bit D3 - ENDECDIS (B3ZS/HDB3 Encoder/Decod-
er-Disable)
This Read/Write bit-field is used to enable or disable
the B3ZS/HDB3 Encoder/Decoder in the
XRT73LC00A.
Writing a “1” to this bit-field disables the B3ZS/HDB3
Encoder. Writing a “0” to this bit-field enables the
B3ZS/HDB3 Encoder.
Command Register - CR2
N
OTE
:
This Encoder performs HDB3 Encoding if the
XRT73LC00A is operating in the E3 Mode. Otherwise, it
performs B3ZS Encoding.
N
OTE
:
If the Analog LOS Detector is disabled, then the
RLOS input pin is only asserted by the DLOS (Digital LOS
Detector).
Bit D1 - DLOSDIS (Digital LOS Disable)
This Read/Write bit-field is used to disable the Digital
LOS Detector.
Writing a “0” to this bit-field enables the Digital LOS
Detector. Writing a “1” to this bit-field disables the
Digital LOS Detector.
N
OTE
:
If the Digital LOS Detector is disabled, then the
RLOS input pin is only asserted by the ALOS (Analog LOS
Detector).
Bit D0 - REQDIS (Receive Equalization Disable)
This Read/Write bit-field is used to either enable or
disable the internal Receive Equalizer in the
XRT73LC00A.
Writing a “0” to this bit-field enables the Internal
Equalizer. Writing a “1” to this bit-field disables the
Internal Equalizer.
5.1.4
Command Register - CR3
Bit D4 - RNRZ (Receive Binary Data)
This Read/Write bit-field is used to configure the
XRT73LC00A to output the received data from the
Remote Terminal in a binary or Dual-Rail format.
Writing a “1” to this bit-field configures the
XRT73LC00A to output data to the Terminal Equip-
ment in a Single-Rail (binary) format via the RPOS
output pin. The RNEG is grounded. A “0” to this bit-
field configures the XRT73LC00A to output data to
the Terminal Equipment in a Dual-Rail format via both
the RPOS and RNEG output pins.
Bit D3 - LOSMUT (Recovered Data Muting during
LOS Condition)
This Read/Write bit-field is used to configure the
XRT73LC00A to NOT output any recovered data
while it is declaring an LOS condition to the terminal
equipment.
Writing a “0” to this bit-field configures the chip to out-
put recovered data even while the XRT73LC00A is
declaring an LOS condition. Writing a “1” to this bit-
field configures the chip to NOT output the recovered
data while an LOS condition is being declared.
N
OTE
:
In this mode, RPOS and RNEG is set to “0” asyn-
chronously.
Bit D2 - RCLK2/LCV (Receive Clock Output 2/Line
Code Violation)
This Read/Write bit-field is used to select the function
of pin 30 (RCLK2/LCV). Pin 30 can be configured to
function as the Line Code Violation output indicator or
as the additional Receive Clock Output (RCLK2).
Writing a “0” to this bit-field configures the pin to func-
tion as the Line Code Violation output pin. Writing a
“1” to this bit-field configures this pin to function as
the RCLK2 output pin.
Bit D1 - RCLK2INV (Invert RCLK2)
This Read/Write bit-field is used to configure the Re-
ceiver in the XRT73LC00A to output the recovered
data on either the rising edge or the falling edge of
the RCLK2 clock signal.
Writing a “0” to this bit-field configures the Receiver to
output the recovered data on the rising edge of the
RCLK2 output signal. Writing a “1” to this bit-field
configures the Receiver to output the recovered data
on the falling edge of the RCLK2 output signal.
Bit D0 - RCLK1INV (Invert RCLK1)
This Read/Write bit-field is used to configure the Re-
ceiver in the XRT73LC00A to output the recovered
data on either the rising edge or the falling edge of
the RCLK1 clock signal.
Writing a “0” to this bit-field configures the Receiver to
output the recovered data on the rising edge of the
RCLK1 output signal. Writing a “1” to this bit-field
configures the Receiver to output the recovered data
on the falling edge of the RCLK1 output signal.
5.1.5
Command Register - CR4
Bit D4 - Reserved
This bit-field has no defined functionality
Bit D3 - STS-1/DS3 Mode Select
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73LC03A | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03AIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC04A | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC04AIV | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73R06 | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73LC00AIV-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 1-Ch DS3, E3, SONET RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73LC00AIVTR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00AIVTR-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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