參數(shù)資料
型號(hào)： XRT73LC00AIV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PQFP44
封裝： 10 X 10 MM, 1.40 MM HEIGHT, TQFP-44
文件頁(yè)數(shù)： 42/53頁(yè)
文件大?。?/td> 376K
代理商： XRT73LC00AIV
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.0
xr
LLB
RLB
ENDECDIS
TAOS
TPDATA
TNDATA
TCLK
PRELIMINARY
39
Figure 29 illustrates the path that the data takes when
the chip is configured to operate in the Analog Local
Loop-Back Mode.
The XRT73LC00A can be configured to operate in
the Analog Local Loop-Back Mode by employing ei-
ther one of the following two steps:
If the XRT73LC00A is operating in the HOST
Mode:
Access the Microprocessor Serial Interface and write
a “1” into the LLB bit-field and a “0” into the RLB bit-
field in Command Register 4.
If the XRT73LC00A is operating in the Hardware
Mode:
The LLB input pin (pin 14) must be set to “High” and
the RLB input pin (pin 15) must be set to “Low”.
N
OTES
:
1. The Analog Local Loop-Back Mode does not work
if the transmitter is turned off via the TXOFF fea-
ture.
2. The XRT73LC00A automatically Declares an LOS
Condition anytime it has been configured to oper-
ate in either the Analog Local Loop-Back or Digital
Local Loop-Back Modes. Consequently, the Muting
-upon -LOS must be disabled prior to configuring
the device to operate in either of these local Loop-
Back modes.
T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
M
ODE
When the XRT73LC00A is configured to operate in
the Digital Local Loop-Back Mode, it ignores any sig-
nals that are input to the RTIP and RRING input pins.
The Transmitting Terminal Equipment transmits clock
and data into the XRT73LC00A via the TPDATA,
TNDATA and TCLK input pins. This data is pro-
cessed through the Transmit Clock Duty Cycle Adjust
PLL and the HDB3/B3ZS Encoder block and then
looped back to the HDB3/B3ZS Decoder block.
Figure 30 illustrates the path that the data takes when
the chip is configured to operate in the Digital Local
Loop-Back Mode.
4.2
F
IGURE
29. T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK
IN
THE
XRT73LC00A
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
RTIP
RRING
REQDIS
RCLK1
RCLK2
RPOS
RNEG
DR/SR
RLOL EXCLK
Device
Monitor
MTIP
MRING
Transmit
Logic
Duty Cycle Adjust
TXLEV
TXOFF
DMO
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Analog Local
Loop-Back Path
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
X
X
1
0
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