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參數(shù)資料
| 型號： | XRT73LC00AIV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | E3/DS3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, TQFP-44 |
| 文件頁數(shù)： | 40/53頁 |
| 文件大小： | 376K |
| 代理商： | XRT73LC00AIV |
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XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.0
xr
PRELIMINARY
37
RCLK1 (or RCLK2) is the Recovered Clock signal
from the incoming Received line signal. These clock
signals are typically 34.368 MHz for E3 applications,
44.736 MHz for DS3 applications and 51.84 MHz for
SONET STS-1 applications.
If the XRT73LC00A received a positive-polarity pulse
in the incoming line signal via the RTIP and RRING
input pins, then the XRT73LC00A pulses the RPOS
output pin “High”. If the XRT73LC00A received a
negative-polarity pulse in the incoming line signal via
the RTIP and RRING input pins, then the
XRT73LC00A pulses the RNEG output pin “High”.
Inverting the RCLK1 or RCLK2 outputs
When using the XRT73LC00A, either of the RCLK1
or RCLK2 signals can be inverted with respect to the
delivery of the RPOS and RNEG output signals to the
Receiving Terminal Equipment. This feature may be
useful for those customers whose Receiving Terminal
Equipment logic design is such that the RPOS and
RNEG data must be sampled on the rising edge of
RCLK1 or RCLK2. Figure 26 illustrates the behavior
of the RPOS, RNEG and RCLK signals when the
RCLK signal has been inverted.
To configure the XRT73LC00A to invert the RCLK1
output signal, the XRT73LC00A must be operating in
the HOST Mode. This configuration can be imple-
mented by accessing the Microprocessor Serial Inter-
face block and writing a “1” into the RCLK1INV bit-
field in Command Register CR3 to invert RCLK1.
The RCLK2 output signal can also be inverted when
the XRT73LC00A is operating in the Hardware Mode
by setting the RCLK2INV input pin “High”.
3.7.1
Routing Single-Rail Format data (Binary
Data Stream) to the Receive Terminal Equipment
To route Single-Rail format data (e.g., a binary data
stream) from the Receive Section of the
XRT73LC00A to the Receiving Terminal Equipment,
do the following:
A.
configure the XRT73LC00A to operate in the
HOST Mode and
F
IGURE
25. H
OW
THE
XRT73LC00A O
UTPUTS
D
ATA
ON
THE
RPOS
AND
RNEG O
UTPUT
P
INS
RCLK1
RPOS
RNEG
F
IGURE
26. T
HE
B
EHAVIOR
OF
THE
RPOS, RNEG
AND
RCLK1 S
IGNALS
W
HEN
RCLK1
IS
I
NVERTED
RCLK1
RPOS
RNEG
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4
D3
D2
D1
D0
RNRZ
LOSMUT
CLK2DIS
RCLK2INV
RCLK1INV
X
X
X
1
1
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| XRT73LC03A | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03AIV | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC04A | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC04AIV | 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73R06 | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73LC00AIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI 1-Ch DS3, E3, SONET RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT73LC00AIVTR | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00AIVTR-F | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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