參數資料
| 型號： | XRT73LC00AIV-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 3/61頁 |
| 文件大小： | 0K |
| 描述： | IC LIU STS1/DS3/E3 SGL 44TQFP |
| 標準包裝： | 160 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應商設備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
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XRT73LC00A
8
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT
22
CS/(DR/SR)
I
Microprocessor Serial Interface - Chip Select/Encoder and Decoder Disable
The function of this input pin depends upon whether the XRT73LC00A is operat-
ing in the HOST or the Hardware Mode.
HOST Mode - Chip Select Input:
The Local Microprocessor must assert this pin (e.g., set it to “0”) in order to
enable communication with the XRT73LC00A via the Microprocessor Serial
Interface.
Hardware Mode - Dual-Rail/Single-Rail Select Input:
Setting this input pin “High” configures the XRT73LC00A to operate in the Dual-
Rail Mode. When the XRT73LC00A is operating in this mode, then the Receive
Section of the LIU IC outputs the Recovered Data via both RPOS and RNEG
output pins.
Setting this input pin “Low” configures the XRT73LC00AXRT73LC00A to oper-
ate in the Single-Rail Mode. When the XRT73LC00A is operating in this mode,
the Receive Section of the LIU IC outputs the Recovered Data via the RPOS
output pin in a binary data stream. No data will output via the RNEG output pin.
23
RLOL
O
Receive Loss of Lock Output Indicator
This output pin toggles “High” if the XRT73LC00A has detected a Loss of Lock
Condition. The XRT73LC00A declares an LOL (Loss of Lock) Condition if the
recovered clock frequency deviates from the Reference Clock frequency (avail-
able at the EXCLK input pin) by more than 0.5%.
NOTE: The RCLK1/2 output pins are sourced by the signal applied at the EXCLK
input pin anytime the XRT73LC00A declares an LOL condition.
24
RLOS
O
Receive Loss of Signal Output Indicator
This output pin toggles “High” if the XRT73LC00A has detected a Loss of Signal
Condition in the incoming line signal.
The criteria the XRT73LC00A uses to declare an LOS Condition depends upon
whether the device is operating in the E3 or DS3/STS-1 Mode.
25
DGND
****
Digital Ground
26
DVDD
****
Digital Power Supply
27
EXCLK
I
External Reference Clock Input:
Apply a line-rate clock signal to this input pin. This signal is a 34.368MHz clock
signal for E3 applications, a 44.736 MHz clock signal for DS3 applications or a
51.84 MHz clock signal for SONET STS-1 applications.
NOTE: This input pin functions as the source of the RxCLK output clock signal
any time the XRT73LC00A declares an LOL condition.
28
RxDGND
****
Receiver Digital Ground
29
RxDVDD
****
Receiver Digital Power Supply
PIN DESCRIPTION
PIN #SYMBOL
TYPE
DESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| XRT73LC03AIV-F | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| XRT73LC04AIV-F | IC LIU E3/DS3/STS-1 4CH 144LQFP |
| XRT73R06IB-F | IC LIU E3/DS3/STS-1 6CH 217BGA |
| XRT73R12IB-L | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| XRT75L00DIV-F | IC LIU E3/DS3/STS-1 SGL 52TQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XRT73LC00AIVTR | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00AIVTR-F | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT73LC00IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73LC03A_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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