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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
66
Bit 2 - LOF (Loss of Frame) Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if a Change in LOF Condition interrupt has occurred since the
last read of this register.
The Receive DS3/E3 Framer block will generate the Change in LOF Condition interrupt in response to either of
the following two occurrences.
1. Whenever the Receive DS3/E3 Framer block transitions from the OOF Condition state into the LOF Condi-
tion state, within the E3 Framing Acquisition/Maintenance algorithm (per
Figure 182).
2. Whenever the Receive DS3/E3 Framer block transitions from the FA1, FA2 Octet Verification state to the
In-frame state, within the E3 Framing Acquisition/Maintenance algorithm (per
Figure 182).Bit 1 - LOS (Loss of Signal) Interrupt Status
This Reset Upon Read bit will be set to "1", if the Receive DS3/E3 Framer block has detected a
Change in the LOS Status condition, since the last time this register was read. This bit-field will be asserted
under either of the following two conditions:
1. When the Receive DS3/E3 Framer block detects the occurrence of an LOS Condition (e.g., the occurrence
of 32 consecutive spaces in the incoming E3 data stream), and
2. When the Receive DS3/E3 Framer block detects the end of an LOS Condition (e.g., when the Receive
DS3/E3 Framer block detects a string 32 bits that does not contain a string of four consecutive "0’s").
The local P can determine the current state of the LOS condition by reading bit 4 of the Rx E3 Configuration
and Status Register (Address = 0x11).
NOTE: For more information in the LOS of Signal (LOS) Alarm, refer to
Bit 0 - AIS Interrupt Status
This Reset Upon Read bit field will be set to "1", if the Receive DS3/E3 Framer block has detected a Change in
the AIS condition, since the last time this register was read. This bit-field will be asserted under either of the
following two conditions:
1. When the Receive DS3/E3 Framer block first detects an AIS Condition in the incoming E3 data stream.
2. When the Receive DS3/E3 Framer block has detected the end of an AIS Condition in the incoming E3 data
stream.
The local P can determine the current state of the AIS condition by reading bit 3 of the Rx E3 Configuration
and Status Register (Address = 0x11).
NOTE: For more information on the AIS Condition, refer to
2.3.3.6
Receive E3 Interrupt Status Register 2 (E3, ITU-T G.832)
Bit 6 - TTB Change Interrupt Status (Receipt of New Trail Trace Buffer Message interrupt)
This Reset-upon-Read bit-field will be set to "1" if a Receipt of New Trail Trace Buffer Message interrupt has
occurred since the last read of this register.
The Receive DS3/E3 Framer block will generate the Receipt of New Trail Trace Buffer Message interrupt, if it
receives an E3 frame in which the value of the TR byte-field is of the form "1xxxxxxxb". A TR byte-field value of
this form is identified as the frame start marker.
RxE3 Interrupt Status Register 2 (Address = 0x15)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
Not Used
TTB
Change
Interrupt
Status
Not Used
FEBE
Interrupt
Status
FERF
Interrupt
Status
BIP-8
Error Interrupt
Status
Framing
Byte Error
Interrupt
Status
RxPld
Mis
Interrupt
Status
RO
RUR
RO
RUR
0
0000
000