XRT72L50
á
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
361
TABLE 68: A LISTING OF THE OVERHEAD BITS WITHIN THE E3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN THE
XRT72L50 IC
OVERHEAD BIT
INTERNALLY GENERATED
ACCESSIBLE VIA THE TRANSMIT OVERHEAD
DATA INPUT INTERFACE
BUFFER/REGISTER
ACCESSIBLE
FA1 - Bit 7
Yes
No
Yes
FA1 - Bit 6
Yes
No
Yes
FA1 - Bit 5
Yes
No
Yes
FA1 - Bit 4
Yes
No
Yes
FA1 - Bit 3
Yes
No
Yes
FA1 - Bit 2
Yes
No
Yes
FA1 - Bit 1
Yes
No
Yes
FA1 - Bit 0
Yes
No
Yes
FA2 - Bit 7
Yes
No
Yes
FA2 - Bit 6
Yes
No
Yes
FA2 - Bit 5
Yes
No
Yes
FA2 - Bit 4
Yes
No
Yes
FA2 - Bit 3
Yes
No
Yes
FA2 - Bit 2
Yes
No
Yes
FA2 - Bit 1
Yes
No
Yes
FA2 - Bit 0
Yes
No
Yes
EM - Bit 7
Yes
No
Yes
EM - Bit 6
Yes
No
Yes
EM - Bit 5
Yes
No
Yes
EM - Bit 4
Yes
No
Yes
EM - Bit 3
Yes
No
Yes
EM - Bit 2
Yes
No
Yes
EM - Bit 1
Yes
No
Yes
EM - Bit 0
Yes
No
Yes
TR - Bit 7
No
Yes
TR - Bit 6
No
Yes
TR - Bit 5
No
Yes
TR - Bit 4
No
Yes
TR - Bit 3
No
Yes
TR - Bit 2
No
Yes
TR - Bit 1
No
Yes