á
XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
386
within the Tx TTB-0 register C6 through C0 are the CRC-7 bits calculated over the contents of all 16 TR bytes,
within the previous Trail Trace Buffer super-frame. The contents of the remaining Trail Trace Buffer registers
(e.g., Tx TTB-1 through Tx TTB-15) will typically contain the 15 ASCII characters required for the E.164
numbering format.
NOTES:
1.
The XRT72L50 Framer IC will not compute the CRC-7 value, to be written into the Tx TTB-0 register. The user’s
system must compute this value prior to writing it into the Tx TTB-0 register.
2.
The user, when writing data into the Tx TTB registers, must take care to insure that only the Tx TTB-0 register
contains an octet with a “1” in the MSB (most significant bit) position. All remaining Tx TTB registers (e.g., Tx
TTB-1 through Tx TTB-15) must contain octets with a “0” in the MSB position. The reason for this cautionary note
is presented in
6.2.5
The Transmit E3 Line Interface Block
The XRT72L50 Framer IC is a digital device that takes E3 payload and overhead bit information from some
terminal equipment, processes this data and ultimately, multiplexes this information into a series of Outbound
E3 frames. However, the XRT72L50 Framer IC lacks the current drive capability to be able to directly transmit
this E3 data stream through some transformer-coupled coax cable with enough signal strength for it to be
received by the remote receiver. Therefore, in order to get around this problem, the Framer IC requires the use
of an LIU (Line Interface Unit) IC.
An LIU is a device that has sufficient drive capability, along with the
necessary pulse-shaping circuitry to be able to transmit a signal through the transmission medium in a manner
that it can be reliably received by the far-end receiver.
Figure 166 presents a circuit drawing depicting the
Framer IC interfacing to an LIU (XRT73L00 DS3/E3/STS-1 Transmit LIU).
The Transmit Section of the XRT72L50 contains a block which is known as the Transmit E3 LIU Interface block.
The purpose of the Transmit E3 LIU Interface block is to take the Outbound E3 data stream, from the Transmit
E3 Framer block, and to do the following:
1. Encode this data into one of the following line codes
a. Unipolar (e.g., Single-Rail)
b. AMI (Alternate Mark Inversion)
c. HDB3 (High Density Bipolar - 3)
FIGURE 166. INTERFACING THE XRT72L50 FRAMER IC TO THE XRT73L00 DS3/E3/STS-1 LIU
VD D
U1
X R T72L50
TxP O S
65
TxN E G
64
TxLineClk
63
DM O
79
ExtL O S
78
RLO L
77
L L OOP
69
R L OOP
70
TA O S
68
TxL ev
67
En coD is
66
Req
71
RxP O S
76
RxNE G
75
RxLineClk
74
MO TO
27
Reset
28
A0
15
A1
16
A2
17
A3
18
A4
19
A5
20
A6
21
A7
22
A8
23
D0
32
D1
33
D2
34
D3
35
D4
36
D5
37
D6
38
D7
39
RDY_DTCK
6
W R_R/W
7
RD_DS
10
CS
8
AL E_ AS
9
In t
13
TxSer/Sn d M sg
45
TxInClk
43
TxF ram e
61
RxS er/RxId le
86
RxClk
88
RxF ram e
90
RxLO S
95
R xOOF
94
RxRed
93
RxA IS
87
NibIntf
25
U2
X R T73L00
TP D A TA
37
TNDA TA
38
TCLK
36
RCLK 1
31
RNE G
32
RP O S
33
TTIP
41
TR IN G
40
MTIP
44
MR IN G
43
RRING
9
RTIP
8
DM O
4
RLO S
24
RLO L
23
LLB
14
RLB
15
TA O S
2
TxL E V
1
E NCO DIS
21
RE Q D IS
12
T1
1:1
1
5
4
8
T2
1:1
1
5
4
8
R1
36
1
2
R2
36
1
2
R6
37.5
1
2
R3
270
1
2
R4
270
1
2
R5
37.5
1
2
C1
0.01uF
1
2
TxSER
TxInClk
N IBBL EIN TF
R ESETB
RTIP
RRING
CS B
RW
DS
AS
TxF ram e
RxS er
RxClk
RxF ram e
RxLO S
R xOOF
RxRE D
RxA IS
A [8:0]
TR IN G
TTIP
IN TB
D[7:0]
IN TB