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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
362
NOTES:
1.
The XRT72L50 contains mask register bits that permit the user to alter the state of the internally generated value
for these bits.
2.
The Transmit LAPD Controller/Buffer can be configured to be the source of the NR or GC bytes, within the
Outbound E3 data stream.
In all, the Transmit Overhead Data Input Interface permits the user to insert overhead data into the Outbound
E3 frames via the following two different methods.
Method 1 - Using the TxOHClk clock signal
Method 2 - Using the TxInClk and the TxOHEnable signals.
TR - Bit 0
No
Yes
MA - Bit 7
Yes
MA - Bit 6
Yes
MA - Bit 5
Yes
MA - Bit 4
Yes
MA - Bit 3
Yes
MA - Bit 2
Yes
MA - Bit 1
Yes
MA - Bit 0
Yes
NR - Bit 7
No
Yes
NR - Bit 6
No
Yes
NR - Bit 5
No
Yes
NR - Bit 4
No
Yes
NR - Bit 3
No
Yes
NR - Bit 2
No
Yes
NR - Bit 1
No
Yes
NR - Bit 0
No
Yes
GC - Bit 7
No
Yes
GC - Bit 6
No
Yes
GC - Bit 5
No
Yes
GC - Bit 4
No
Yes
GC - Bit 3
No
Yes
GC - Bit 2
No
Yes
GC - Bit 1
No
Yes
GC - Bit 0
No
Yes
TABLE 68: A LISTING OF THE OVERHEAD BITS WITHIN THE E3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN THE
XRT72L50 IC
OVERHEAD BIT
INTERNALLY GENERATED
ACCESSIBLE VIA THE TRANSMIT OVERHEAD
DATA INPUT INTERFACE
BUFFER/REGISTER
ACCESSIBLE