XRT72L50
á
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
37
2.2
Interfacing the XRT72L50 DS3/E3 Framer to the Local C/P via the Microprocessor Interface
Block
The Microprocessor Interface block within the Framer is very flexible and provides the following options to the
user.
To interface the Framer to a C/P over an 8-bit wide bi-directional data bus.
To interface the Framer to an Intel-type or Motorola-type C/P.
To transfer data between the Framer IC and the C/P via the Programmed I/O or Burst Mode
2.2.1
Interfacing the XRT72L50 DS3/E3 Framer to the Microprocessor over an 8 bit wide bi-
directional Data Bus
In general, interfacing the Framer to an 8-bit C/P is straight-forward because all of the registers except the
PMON registers (as described below) within the Framer are 8-bits wide. Further, in this mode the C/P can
read or write data into both even and odd numbered addresses within the Framer address space.
Performance Monitor (PMON) Registers
The XRT72L50 DS3/E3 Framer consists of the following PMON Registers.
PMON LCV Event Count Register
PMON Framing Error Event Count Register
PMON Received FEBE Event Count Register
PMON Parity Error Event Count Register
Unlike most of the registers, the PMON registers are 16-bits wide.
Table 4 lists each of these PMON registers
as consisting of two 8-bit registers. One of these 8-bit register is labeled MSB (Most Significant Byte) and the
other register is labeled LSB (Least Significant Byte). An 8-bit PMON MSB Register reading, concatenated
with its companion 8-bit LSB PMON Register, yields the full 16-bit expression within that PMON Register.
An 8-bit C/P has to perform two consecutive read operations in order to read in the full 16-bit expression
contained within a given PMON register. These PMON Registers are Reset-Upon-Read registers. The entire
16-bit contents within a given PMON Register is reset as soon as an 8-bit C/P reads in either byte of this
two-byte (e.g., 16 bit) expression. The unread companion byte is placed in the PMON Holding register as
detailed below.
For example, consider that an 8-bit C/P needs to read in the PMON LCV Event Count Register. In order to
accomplish this task, the 8-bit C/P is going to have to read in the contents of PMON LCV Event Count
Register - MSB (located at Address = 0x50) and the contents of the PMON LCV Event Count Register - LSB
TABLE 3: DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS - OPERATING IN THE MOTOROLA MODE
PIN NAME
EQUIVALENT PIN
IN
MOTOROLA
ENVIRONMENT
TYPE
DESCRIPTION
ALE_AS
AS
I
Address Strobe: This active-low signal is used to latch the contents on the
address bus input pins A[8:0] into the Microprocessor Interface circuitry. The
contents of the Address Bus are latched into the Framer on the rising edge of
the ALE_AS signal.
RD_DS
DS
I
Data Strobe: This signal latches the contents of the bi-directional data bus
pins into the Addressed Register during a Write Cycle.
WR_R/W
R/W
I
Read/Write Input: When this pin is "High" it indicates a Read Cycle. When
this pin is "Low" it indicates a Write cycle.
RDY_DTCK
DTACK
O
Data Transfer Acknowledge: The Framer asserts DTACK in order to inform
the CPU that the present READ or WRITE cycle is complete. The 68000 fam-
ily of CPUs requires this signal from its peripheral devices in order to quickly
and properly complete a READ or WRITE cycle.