參數(shù)資料
型號: XRS10L120IV
廠商: EXAR CORP
元件分類: 數(shù)字信號處理外設(shè)
英文描述: SERIAL ATA II: 1:2 PORT MULTIPLIER
中文描述: DSP-MULTIPLIER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, LQFP-100
文件頁數(shù): 39/52頁
文件大?。?/td> 399K
代理商: XRS10L120IV
PRELIMINARY
XRS10L120
37
REV. P1.0.1
SERIAL ATA II: 1:2 PORT MULTIPLIER
4.3
XRS10L120 Device Generic Registers
This section outlines generic registers relating to the XRS10L120 as a whole. These registers are accessed
through MDIO device 0.
1.0087
2.0087
7:6
SIcomfinish[1:0]
SO01comfinish[1:0]
RO/LH
00
Signal generation initiated by comtype has
finished
5:4
SIsigValid[1:0]
SO01sigValid[1:0]
RO/LH
00
Valid signal received on lane
3:2
SICOMWAKE[1:0]
SO01COMWAKE[1:0]
RO/LH
00
COMWAKE Sequence received on lane
1:0
SICOMINIT[1:0]
SO01COMINIT[1:0]
RO/LH
00
COMINIT Sequence received on lane
1.0088
2.0088
7:6
Reserved
RO
-
Reserved
5:4
SIRXErr[1:0]
SO01RXErr[1:0]
RO/LH
00
PRBS error on lane. Self clearing
3:2
SIrcvAbsent[1:0]
SO01rcvAbsent[1:0]
RO/LH
00
No Receiver present on lane
1:0
SIrcvPresent[1:0]
SO01rcvPresent[1:0]
RO/LH
00
Receiver detected on lane
T
ABLE
14: R
ESET
C
ONTROL
S
IGNALS
A
DDRESS
H
EX
B
IT
(
S
)
N
AME
RW
R
ESET
V
ALUE
D
ESCRIPTION
0.0000
7:2
Reserved
RO
-
Reserved
1
simflag
RW
0
speed up flag for simulation only
0
rseqstart
RW/SC
0
setting starts up reset controller. Self clear-
ing
0.0003
0.0002
7:0
override_reg[15:0]
RW
0x00
0x00
Override register for resets
[15] – ebables all overrides
[14:9] spares
[8] – rcal reset
[7] – device macro1
[6] – device macro0
[5] – selector and multiplier
[4] – device gasket 1
[3] – device gasket 0
[2] – host gasket
[1] – host macro
[0] – rcal enable
0.0004
3:0
resetPLLB_reg[3:0]
RW
0xf
Resets the PLL portion of the macros.
T
ABLE
13: B
LOCK
C
ONTROL
S
IGNALS
(MDIO D
EVICES
1
AND
2)
A
DDRESS
H
EX
B
IT
(
S
)
N
AME
RW
R
ESET
V
ALUE
D
ESCRIPTION
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