參數(shù)資料
型號： XRS10L120IV
廠商： EXAR CORP
元件分類： 數(shù)字信號處理外設(shè)
英文描述： SERIAL ATA II: 1:2 PORT MULTIPLIER
中文描述： DSP-MULTIPLIER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LQFP-100
文件頁數(shù)： 3/52頁
文件大?。?/td> 399K
代理商： XRS10L120IV
PRELIMINARY
XRS10L120
I
REV. P1.0.0
SERIAL ATA II: 1:4 PORT MULTIPLIER
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................ 1
O
VERVIEW
OF
PORT
MULTIPLIER
LOGIC
.......................................................................................................... 1
STANDARDS
COMPLIANCE
.............................................................................................................................. 1
APPLICATIONS.......................................................................................................................................... 1
FEATURES
.................................................................................................................................................... 1
General Features ....................................................................................................................................................... 1
Port Multiplier Logic Features..................................................................................................................................... 1
Test and Control Features.......................................................................................................................................... 1
High Speed I/O Features............................................................................................................................................ 2
Physical Features....................................................................................................................................................... 2
Application Example................................................................................................................................................... 2
F
IGURE
1. S
YSTEM
B
LOCK
D
IAGRAM
FOR
XRS10L120
IN
A
D
RIVE
E
NCLOSURE
A
PPLICATION
........................................................... 2
TABLE OF CONTENTS.....................................................................................................
I
1.0 PIN DESCRIPTIONS................................................................................................................................ 3
F
IGURE
2. P
INOUT
OF
THE
XRS10L120........................................................................................................................................... 3
T
ABLE
1: XRS10L120 P
IN
D
ESCRIPTIONS
....................................................................................................................................... 4
2.0 FUNCTIONAL DESCRIPTION................................................................................................................. 6
F
IGURE
3. XRS10L120 I
NTERFACES
................................................................................................................................................ 6
F
IGURE
4. XRS10L120 B
LOCK
D
IAGRAM
......................................................................................................................................... 6
2.1 OUT OF BAND FEATURE................................................................................................................................... 7
F
IGURE
5. COMWAKE
AND
COMRESET/COMINIT S
EQUENCES
................................................................................................... 7
F
IGURE
6. E
XAMPLE
OOB S
EQUENCE
.............................................................................................................................................. 7
2.2 POWER DOWN MODES ..................................................................................................................................... 8
2.3 SPEED NEGOTIATION ....................................................................................................................................... 8
F
IGURE
7. S
ERIAL
ATA S
PEED
N
EGOTIATION
................................................................................................................................... 8
2.4 PORT MULTIPLIER IMPLEMENTATION............................................................................................................ 9
F
IGURE
8. P
ORT
SELECTION
S
IGNAL
- T
RANSMITTED
COMRESET S
IGNALS
..................................................................................... 9
2.5 TRANSMISSION FROM A HOST TO A DEVICE................................................................................................ 9
2.5.1 TRANSMISSION FROM A DEVICE TO A HOST ......................................................................................................... 10
2.6 CLOCKING ........................................................................................................................................................ 11
T
ABLE
2: PLL D
IVIDE
F
ACTORS
...................................................................................................................................................... 11
2.6.1 SPREAD SPECTRUM CLOCKING............................................................................................................................... 11
F
IGURE
9. S
PREAD
S
PECTRUM
C
LOCKING
...................................................................................................................................... 11
2.7 TEST AND LOOPBACK MODES...................................................................................................................... 12
2.7.1 HOST SIDE LOOPBACK MODES................................................................................................................................ 12
Shallow Host Loopback Mode.................................................................................................................................. 12
F
IGURE
10. S
HALLOW
H
OST
L
OOPBACK
M
ODE
............................................................................................................................... 12
Deep Host Loopback Mode...................................................................................................................................... 12
F
IGURE
11. D
EEP
H
OST
L
OOPBACK
M
ODE
..................................................................................................................................... 12
2.7.2 DEVICE SIDE LOOPBACK MODES ............................................................................................................................ 13
Shallow Device Loopback Mode .............................................................................................................................. 13
F
IGURE
12. S
HALLOW
D
EVICE
L
OOPBACK
M
ODE
............................................................................................................................ 13
Deep Device Loopback Mode .................................................................................................................................. 13
F
IGURE
13. D
EEP
D
EVICE
L
OOPBACK
M
ODE
.................................................................................................................................. 13
3.0 ELECTRICAL SPECIFICATIONS.......................................................................................................... 14
3.1 SERIAL ATA SPECIFICATIONS....................................................................................................................... 14
3.1.1 SERIAL ATA TRANSMITTER....................................................................................................................................... 14
F
IGURE
14. S
ERIAL
ATA E
QUIVALENT
O
UTPUT
C
IRCUIT
................................................................................................................. 14
F
IGURE
15. E
FFECTS
OF
T
RANSMIT
P
RE
-E
MPHASIS
........................................................................................................................ 15
F
IGURE
16. T
RANSMIT
E
YE
M
ASK
FOR
S
ERIAL
ATA O
UTPUT
.......................................................................................................... 15
Serial ATA Receiver................................................................................................................................................. 16
F
IGURE
17. S
ERIAL
ATA E
QUIVALENT
I
NPUT
C
IRCUIT
..................................................................................................................... 16
F
IGURE
18. R
ECEIVE
E
YE
M
ASK
FOR
S
ERIAL
ATA I
NPUT
................................................................................................................ 16
T
ABLE
3: S
ERIAL
ATA L
INK
S
PECIFICATIONS
.................................................................................................................................. 17
3.2 CMOS INTERFACE........................................................................................................................................... 18
T
ABLE
4: CMOS I/O S
PECIFICATIONS
............................................................................................................................................ 18
3.3 MDIO INTERFACE............................................................................................................................................. 18
F
IGURE
19. R
EPRESENTATIVE
MDIO C
IRCUIT
................................................................................................................................ 18
F
IGURE
20. MDIO I
NPUT
AND
O
UTPUT
W
AVEFORMS
...................................................................................................................... 19
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XRS10L120IV-F 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
XRS10L140 制造商:EXAR 制造商全稱:EXAR 功能描述:SERIAL ATA II: PORT MULTIPLIER
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XRS10L140IV 制造商:EXAR 制造商全稱:EXAR 功能描述:SERIAL ATA II: PORT MULTIPLIER
XRS10L140IV-F 功能描述:計(jì)數(shù)器 IC RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel
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