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參數(shù)資料
| 型號： | XRS10L120IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | SERIAL ATA II: 1:2 PORT MULTIPLIER |
| 中文描述： | DSP-MULTIPLIER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LQFP-100 |
| 文件頁數(shù)： | 10/52頁 |
| 文件大?。?/td> | 399K |
| 代理商： | XRS10L120IV |
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XRS10L120
PRELIMINARY
8
SERIAL ATA II: 1:2 PORT MULTIPLIER
REV. P1.0.1
2.2
Power Down Modes
Each Serial ATA link within the XRS10L120 features independent full support for the 3 defined Serial ATA
power modes, as follows:
Active: All parts of the link are active. All power-down signals are de-asserted.
Partial: In partial mode, the input and output pipelines are shut down, but the PLL and the OOB generation
circuits are active.
Slumber: In slumber mode, the PLL is also shut down, saving additional power but adding latency on exit.
The XRS10L120 also provides full support for power management commands from connected hosts and
devices, as outlined by the Serial ATA II port multiplier specifications.
If the PhyRdy signal is not present between the host and the XRS10L120, the XRS10L120 will power down the
PHY connected to the host and squelch the device transmitters. OOB signals will still be propagated between
the host and the XRS10L120.
Power management requests from a host port, as specified by a PMREQ primitive, will propagate to all active
device ports. In such a condition, the XRS10L120 will respond with a PMACK or PMNAK primitive,
appropriately modify the power setting of the link with the host, and then propagate the request to each device
that has PhyRdy set. The link within the XRS10L120 to each device that responds with a valid PMACK signal
will be appropriately modified to reflect the new power setting.
Power management requests from a device port, as specified by a PMREQ primitive, will only affect the link
between that device and the XRS10L120. In such a condition, the XRS10L120 will respond with a PMACK or
PMNAK primitive, and modify the link to reflect the requested power state.
2.3
Speed Negotiation
The XRS10L120 will automatically perform speed negotiation with the host and devices in order to verify
whether the second generation Serial ATA 3.0 Gbps data rate is available or whether the system will need to
fall back upon the first generation Serial ATA 1.5 Gbps data rate. Speed negotiation is performed on an
independent basis by each of the dual-channel macros. To perform speed negotiation with a downstream
device, the XRS10L120 will first perform a COMRESET/COMINIT handshake with the device and then
performs a calibrate/COMWAKE handshake. Following receipt of the device COMWAKE signal, the
XRS10L120 will continually send out a D10.2 signal while awaiting receipt of the device ALIGN primitive.
Depending on the speed of the ALIGN primitive, the XRS10L120 will be able to determine the PHY generation
of the device, and provide the appropriate 1.5 Gbps or 3.0 Gbps ALIGN primitive in return to the device, thus
completing speed negotiation. This process is outlined in
Figure 7
.
F
IGURE
7. S
ERIAL
ATA S
PEED
N
EGOTIATION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRS10L120IV-F | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| XRS10L140 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SERIAL ATA II: PORT MULTIPLIER |
| XRS10L140ES | 功能描述:計(jì)數(shù)器 IC RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| XRS10L140IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:SERIAL ATA II: PORT MULTIPLIER |
| XRS10L140IV-F | 功能描述:計(jì)數(shù)器 IC RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
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