參數(shù)資料
型號(hào): XRS10L120IV
廠商: EXAR CORP
元件分類: 數(shù)字信號(hào)處理外設(shè)
英文描述: SERIAL ATA II: 1:2 PORT MULTIPLIER
中文描述: DSP-MULTIPLIER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, LQFP-100
文件頁數(shù): 28/52頁
文件大?。?/td> 399K
代理商: XRS10L120IV
XRS10L120
PRELIMINARY
26
SERIAL ATA II: 1:2 PORT MULTIPLIER
REV. P1.0.1
N.0013
N.0033
7:0
rcvdetdelay1[10:0]
(lower 8 bits)
0
Invert outgoing rxpclk for external use
7:3
Reserved
1
Invert incoming rxpclk for internal use
2:0
rcvdetdelay1[10:0]
(upper 3 bits)
0
line loopback fifo rxpclk flip
7
orxpclkflip
0
Invert outgoing txpclk for external use
6
irxpclkflip
0
Invert incoming txpclk for internal use
5
rxpclkflip
000
Selection for clock onto clockTest pin
000 = disable
001 = txpclk[0]
010 = rxclk[0]
011 = sysclk
100 = SSCtrig
other = reserved
Only clkTestSel0 is active; clkTestSel1 is a no-
connect
N.0014
N.0034
4
otxpclkflip
RO
-
Reserved
3
itxpclkflip
011
Number of idles required before declaring a
COM* match
2:0
clkTestSel0[2:0]
clkTestSel1[2:0]
100
Number of bursts required before declaring a
COM* match
N.0015
N.0035
7:6
Reserved
RO
-
Reserved
5:3
nidleCmin[2:0]
011
Divider selection for sysclk-> sysclk25
000 = divide by 1 (sysclk is 25MHz)
001 = divide by 2 (sysclk is 50MHz)
010 = divide by 3 (sysclk is 75MHz)
011 = divide by 4 (sysclk is 100MHz)
100 = divide by 5 (sysclk is 125MHz)
101 = divide by 6 (sysclk is 150MHz)
110 = divide by 10 (sysclk is 250MHz)
111 = divide by 12 (sysclk is 300MHz)
2:0
nburstCmin[2:0]
0xf
number of bursts in com* sequence
N.0017
N.0016
N.0037
N.0036
7
Reserved
RO
-
PRBS error count
Upper byte read clears both upper and lower
bytes
T
ABLE
9: T
RANSMIT
/R
ECEIVE
L
ANE
R
EGISTERS
(MDIO D
EVICE
1
AND
2)
A
DDRESS
H
EX
B
IT
(
S
)
N
AME
R/W
D
EFAULT
D
ESCRPTION
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