參數(shù)資料
型號(hào)： XRS10L120IV
廠商： EXAR CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： SERIAL ATA II: 1:2 PORT MULTIPLIER
中文描述： DSP-MULTIPLIER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LQFP-100
文件頁(yè)數(shù)： 23/52頁(yè)
文件大?。?/td> 399K
代理商： XRS10L120IV
PRELIMINARY
XRS10L120
21
REV. P1.0.1
SERIAL ATA II: 1:2 PORT MULTIPLIER
4.0
REGISTERS DESCRIPTION
The XRS10L120 provides a variety of registers for the purpose of device configuration, testing and monitoring.
These registers are accessed through the MDIO interface, outlined in
“Section 3.3, MDIO Interface” on
page 18
. The entire register set is described in this section.
4.1
Register Overview
The XRS10L120 port address is hardwired to 0; this field should be set to 0 in all packets.The XRS10L120
contains three identical instantiations of a dual Serial ATA PHY macro. A common set of registers exists within
each of these macros, and are outlined in
“Section 4.2, Macro Registers” on page 22
. MDIO device
designations 1-3 are used for each of these three macros as shown in Table 8. Registers relating to the
XRS10L120 as a whole are outlined in
“Section 4.3, XRS10L120 Device Generic Registers” on page 37
and make use of MDIO device 0.
The XRS10L120 registers are arranged as 8-bit fields with 8-bit addresses. These are mapped into the 16-bit
MDIO address and data fields by setting the most significant byte of each to be 0. An example mapping from a
macro address/data combination to an MDIO address & data combination is shown in Table 9+
N
OTE
:
The unused upper 3 bits in FBDIV are also set to 0 during MDIO writes and are undefined during MDIO reads.
In the description of each register field, there is an entry describing its read/write status. This may fall into one
of the following categories:
R/W- register field is read/write
RO - register field is read only
LL - Latching Low - Used with bits that monitor some state internal to the XRS10L120. When the condition
for the bit to go low is reached, the bit stays low until the next time it is read. Once it is read, its value reverts
to the cur-rent state of the condition it monitors.
LH - Latching High - When the condition for the bit to go high is reached, the bit stays high until the next time
it is read. Once it is read, its value reverts to the current state of the condition it monitors.
SC - When an SC bit is set, some action is initiated; once the action is complete, the bit is cleared.
T
ABLE
7: MDIO D
EVICE
D
ESIGNATIONS
MDIO D
EVICE
D
ESIGNATION
M
ACRO
R
ELEVANT
P
INS
0
XRS10L120 Device Generic Registers
N/A
1
Serial ATA Input Macro
SI0
*
2
Serial ATA Output Macro 0
SO0, SO1
*
Transmit/Receive Lane 1 registers are not applicable for MDIO device 1
.
T
ABLE
8: MDIO A
DDRESSING
M
ACRO
A
DDRESS
M
ACRO
D
ATA
MDIO A
DDRESS
MDIO D
ATA
0x40
abcde
0x0040
00000000000abcde
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