參數(shù)資料
型號: XRP7740ILBTR-F
廠商: Exar Corporation
文件頁數(shù): 14/28頁
文件大?。?/td> 1610K
描述: IC REG 5OUT BCK/LINEAR 40TQFN
產(chǎn)品變化通告: Packing Change 15/Oct/2010
標準包裝: 3,000
系列: PowerXR
拓撲: 降壓(降壓)同步(4),線性(LDO)(1)
功能: 任何功能
輸出數(shù): 5
頻率 - 開關(guān): 1.5MHz
電壓/電流 - 輸出 1: 控制器
電壓/電流 - 輸出 2: 控制器
電壓/電流 - 輸出 3: 控制器
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 6.5 V ~ 20 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN(6x6)
包裝: 帶卷 (TR)
配用: 1016-1352-ND - EVAL BOARD FOR XRP7740
1016-1344-ND - IN-SOCKET PROG BRD VIA USB/GUI
X
X
R
R
P
P
7
7
7
7
0
0
8
8
 
 
a
a
n
n
d
d
 
 
X
X
R
R
P
P
7
7
7
7
4
4
0
0
 
 
Q
Q
u
u
a
a
d
d
 
 
C
C
h
h
a
a
n
n
n
n
e
e
l
l
 
 
D
D
i
i
g
g
i
i
t
t
a
a
l
l
 
 
P
P
W
W
M
M
 
 
S
S
t
t
e
e
p
p
 
 
D
D
o
o
w
w
n
n
 
 
C
C
o
o
n
n
t
t
r
r
o
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?2012 Exar Corporation
14/28
Rev. 1.2.2
 
Fig. 190: VCCA (green) Startup Waveform 
STANDBY LOW DROP-OUT REGULATOR
This 100mA low drop-out regulator can be programmed as 3.3V or 5V in SET_STBLDO_EN_CONFIG
register. Its output is seen on the LDOOUT Pin. This LDO is fully controllable via the Enable Pin
(configured to turn on as soon as power is applied), a GPIO, and/or I
2
C communication.
The standby LDO should be bypassed with a minimum of 2.2uF ceramic capacitor.
ENABLING, DISABLING AND RESET
The XRP7708 is enabled via raising the ENABLE Pin high. The chip can then be disabled by
lowering the same ENABLE Pin. There is also the capability for resetting the Chip via an I
2
C
SOFTRESET Command.
For enabling a specific channel, there are several ways that this can be achieved. The chip can be
configured to enable a channel at start-up as the default configuration residing in the non-volatile
configuration memory of the IC. The channels can also be enabled using GPIO pins and/or an I
2
C
Bus   serial   command.   The   registers   that   control   the   channel   enable   functions   are   the
SET_EN_CONFIG and SET_CH_EN_I2C.
INTERNAL GATE DRIVERS
The XRP7708 integrates Internal Gate Drivers for all 4 PWM channels. These drivers are optimized
to drive both high-side and low side N-MOSFETs for synchronous operation. Both high side and low
side drivers have the capability of driving 1 nF load with 30 ns rise and fall time. The drivers have
built-in non-overlapping circuitry to prevent simultaneous conduction of the two MOSFETs.
FAULT HANDLING
While the chip is operating there are four different types of fault handling:
"    Under Voltage Lockout (UVLO) monitors the input voltage to the chip, and the chip will
shutdown all channels if the voltage drops to critical levels.
"    Over Temperature Protection (OTP) monitors the temperature of the chip, and the chip
will shutdown all channels if the temperature rises to critical levels.
"    Over Voltage Protection (OVP) monitors the voltage of channel and will shutdown the
channel if it surpasses its voltage threshold.
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