參數(shù)資料
型號： XRM48L950ZWTT
廠商： Texas Instruments
文件頁數(shù)： 52/176頁
文件大小： 0K
描述： MCU 16/32Bit FLASH 3MB 337NFBGA
標準包裝： 1
系列： Hercules™ ARM® RM4x
應用： 工業(yè)安全，醫(yī)療
核心處理器： ARM? Cortex? - R4F
程序存儲器類型： 閃存（3MB）
控制器系列： RM4
RAM 容量： 256K x 8
接口： CAN，以太網(wǎng)，I²C，LIN，MibSPI，SCI，SPI，USB
輸入/輸出數(shù)： 120
電源電壓： 1.14 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 337-LFBGA
包裝： 托盤
供應商設備封裝： 337-NFBGA（16x16）
其它名稱： 296-29390
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
5.9
Multi-Buffered / Standard Serial Peripheral Interface
The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display
drivers, and analog-to-digital converters.
5.9.1
Features
Both Standard and MibSPI modules have the following features:
16-bit shift register
Receive buffer register
5-bit baud clock generator
SPICLK can be internally-generated (master mode) or received from an external clock source (slave
mode)
Each word transferred can have a unique format
SPI I/Os not used in the communication can be used as digital input/output signals
Table 5-18. MibSPI/SPI Configurations
MibSPIx/SPIx
I/Os
MibSPI1
MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA
MibSPI3
MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MibSPI5
MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA
SPI2
SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA
SPI4
SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA
5.9.2
MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a
16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each.
5.9.3
MibSPI Transmit Trigger Events
Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event
and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low
level at a selectable trigger source. For example, up to 15 trigger sources are available which can be
utilized by each transfer group. These trigger options are listed in Table 5-19 for MIBSPI1, Section 5.9.3.2
for MIBSPI3 and Section 5.9.3.3 for MibSPI5.
Copyright 2012–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
145
Product Folder Links: RM48L950 RM48L750 RM48L550
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