參數(shù)資料
型號: XRM48L950ZWTT
廠商: Texas Instruments
文件頁數(shù): 15/176頁
文件大?。?/td> 0K
描述: MCU 16/32Bit FLASH 3MB 337NFBGA
標(biāo)準(zhǔn)包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 120
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 337-LFBGA
包裝: 托盤
供應(yīng)商設(shè)備封裝: 337-NFBGA(16x16)
其它名稱: 296-29390
TRST
TMS
TCK
TDI
TDO
RTCK
ICEPICK_C
BoundaryScan
BSR/BSDL
BoundaryScanI/F
SecondaryTap0
DAP
Debug APB
Debug
ROM1
APBslave
Cortex
R4F
APBMux
AHB-AP
POM
ETM
TPIU
toSCR1via A2A
from
PCR1/Bridge
SecondaryTap1
DMM
RTP
TAP 0
TAP 1
SecondaryTap2
AJSM
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.21 Debug Subsystem
4.21.1 Block Diagram
The device contains an ICEPICK module to allow JTAG access to the scan chains.
Figure 4-19. Debug Subsystem Block Diagram
NOTE
The ETM, RTP and DMM exist in silcon, but are not supported in the PGE package.
4.21.2 Debug Components Memory Map
Table 4-37. Debug Components Memory Map
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
FRAME CHIP
FRAME
ACTUA
MODULE NAME
UNIMPLEMENTED LOCATIONS IN
SELECT
SIZE
L SIZE
START
END
FRAME
CoreSight Debug
CSCS0
0xFFA0_0000
0xFFA0_0FFF
4KB
Reads: 0, writes: no effect
ROM
Cortex-R4F
CSCS1
0xFFA0_1000
0xFFA0_1FFF
4KB
Reads: 0, writes: no effect
Debug
ETM-R4
CSCS2
0xFFA0_2000
0xFFA0_2FFF
4KB
Reads: 0, writes: no effect
CoreSight TPIU
CSCS3
0xFFA0_3000
0xFFA0_3FFF
4KB
Reads: 0, writes: no effect
Copyright 2012–2013, Texas Instruments Incorporated
System Information and Electrical Specifications
111
Product Folder Links: RM48L950 RM48L750 RM48L550
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