參數(shù)資料
型號: XRM48L950ZWTT
廠商: Texas Instruments
文件頁數(shù): 132/176頁
文件大?。?/td> 0K
描述: MCU 16/32Bit FLASH 3MB 337NFBGA
標準包裝: 1
系列: Hercules™ ARM® RM4x
應用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網,I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 120
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 337-LFBGA
包裝: 托盤
供應商設備封裝: 337-NFBGA(16x16)
其它名稱: 296-29390
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.4
Warm Reset (nRST)
This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset
condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the
output buffer is implemented as an open drain (drives low only). To ensure an external reset is not
arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. It also has an internal pullup
4.4.1
Causes of Warm Reset
Table 4-5. Causes of Warm Reset
DEVICE EVENT
SYSTEM STATUS FLAG
Power-Up Reset
Exception Status Register, bit 15
Oscillator fail
Global Status Register, bit 0
PLL slip
Global Status Register, bits 8 and 9
Watchdog exception / Debugger reset
Exception Status Register, bit 13
CPU Reset (driven by the CPU STC)
Exception Status Register, bit 5
Software Reset
Exception Status Register, bit 4
External Reset
Exception Status Register, bit 3
4.4.2
nRST Timing Requirements
Table 4-6. nRST Timing Requirements
PARAMETER
MIN
MAX
UNIT
tv(RST)
Valid time, nRST active after
2276tc(OSC)
(1)
ns
nPORRST inactive
Valid time, nRST active (all other
32tc(VCLK)
System reset conditions)
tf(nRST)
475
2000
ns
Filter time nRST pin;
pulses less than MIN will be
filtered out, pulses greater than
MAX will generate a reset
(1)
Assumes the oscillator has started up and stabilized before nPORRST is released .
Copyright 2012–2013, Texas Instruments Incorporated
System Information and Electrical Specifications
59
Product Folder Links: RM48L950 RM48L750 RM48L550
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