參數(shù)資料
型號(hào): XRM48L950ZWTT
廠商: Texas Instruments
文件頁數(shù): 19/176頁
文件大小: 0K
描述: MCU 16/32Bit FLASH 3MB 337NFBGA
標(biāo)準(zhǔn)包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲(chǔ)器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 120
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 337-LFBGA
包裝: 托盤
供應(yīng)商設(shè)備封裝: 337-NFBGA(16x16)
其它名稱: 296-29390
t
r(ETM)
t
h(ETM)
t
l(ETM)
t
f(ETM)
t
cyc(ETM)
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.21.7 Embedded Trace Macrocell (ETM-R4)
The device contains a ETM-R4 module with a 32-bit internal data port. The ETM-R4 module is connected
to a TPIU with a 32-bit data bus; the TPIU provides a 35-bit (32-bit data, 3-bit control) external interface
for trace. The ETM-R4 is CoreSight compliant and follows the ETM v3 specification; for more details see
ARM CoreSight ETM-R4 TRM specification.
4.21.7.1 ETM TRACECLKIN Selection
The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The
selection is done by the EXTCTRLOUT[1:0] control bits of the TPIU; the default is '00'. The address of this
register is TPIU base address + 0x404.
Before you begin accessing TPIU registers, TPIU should be unlocked via coresight key and 1 or 2 should
be written to this register.
Table 4-41. TPIU / TRACECLKIN Selection
EXTCTRLOUT[1:0]
TPIU/TRACECLKIN
00
tied-zero
01
VCLK
10
ETMTRACECLKIN
11
tied-zero
4.21.7.2 Timing Specifications
Figure 4-22. ETMTRACECLKOUT Timing
Table 4-42. ETMTRACECLK Timing
Parameter
MIN
MAX
Description
tcyc(ETM)
t(HCLK) * 4
Clock period
tl(ETM)
20ns
Low pulse width
th(ETM)
20ns
High pulse width
tr(ETM)
3ns
Clock and data rise time
tf(ETM)
3ns
Clock and data fall time
Copyright 2012–2013, Texas Instruments Incorporated
System Information and Electrical Specifications
115
Product Folder Links: RM48L950 RM48L750 RM48L550
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