參數(shù)資料
型號: XRM48L950PGET
廠商: Texas Instruments
文件頁數(shù): 28/176頁
文件大小: 0K
描述: MCU 16/32Bit FLASH 3MB 144LQFP
標(biāo)準(zhǔn)包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲(chǔ)器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 64
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
包裝: 托盤
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
其它名稱: 296-29389
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
Programmable interrupt threshold counter is available for each group
Programmable magnitude threshold interrupt for each group for any one channel
Option to read either 8-bit, 10-bit or 12-bit values from memory regions
Single or continuous conversion modes
Embedded self-test
Embedded calibration logic
Enhanced power-down mode
Optional feature to automatically power down ADC core when no conversion is in progress
External event pin (ADEVT) programmable as general-purpose I/O
5.2.2
Event Trigger Options
The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3
groups can be configured to be hardware event-triggered. In that case, the application can select from
among 8 event sources to be the trigger for a group's conversions.
5.2.2.1
Default MIBADC1 Event Trigger Hookup
Table 5-3. MIBADC1 Event Trigger Hookup
Event #
Source Select Bits For G1, G2 Or Event
Trigger
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
1
000
ADEVT
2
001
N2HET1[8]
3
010
N2HET1[10]
4
011
RTI compare 0 interrupt
5
100
N2HET1[12]
6
101
N2HET1[14]
7
110
GIOB[0]
8
111
GIOB[1]
NOTE
For ADEVT, N2HET1 and GIOB trigger sources, the connection to the MibADC1 module
trigger input is made from the output side of the input buffer. This way, a trigger condition
can be generated either by configuring the function as output onto the pad (via the mux
control), or by driving the function from an external trigger source as input. If the mux control
module is used to select different functionality instead of the ADEVT, N2HET1[x] or GIOB[x]
signals, then care must be taken to disable these signals from triggering conversions; there
is no multiplexing on the input connections.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
5.2.2.2
Alternate MIBADC1 Event Trigger Hookup
Table 5-4. Alternate MIBADC1 Event Trigger Hookup
Event #
Source Select Bits for G1, G2 or Event
Trigger
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
1
000
ADEVT
2
001
N2HET2[5]
Copyright 2012–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
123
Product Folder Links: RM48L950 RM48L750 RM48L550
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