參數(shù)資料
型號: XRM48L950PGET
廠商: Texas Instruments
文件頁數(shù): 163/176頁
文件大小: 0K
描述: MCU 16/32Bit FLASH 3MB 144LQFP
標準包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 64
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
包裝: 托盤
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
其它名稱: 296-29389
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.13.2 On-Chip SRAM Auto Initialization
This microcontroller allows some of the on-chip memories to be initialized to zero via the Memory
Hardware Initialization mechanism in the System module. This hardware mechanism allows an application
to program the memory arrays with error detection capability to a known state based on their error
detection scheme (odd/even parity or ECC).
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects
the memories that are to be initialized.
For more information on these registers see the device specific technical reference manual.
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in
Table 4-26. Memory Initialization
ADDRESS RANGE
CONNECTING MODULE
MSINENA REGISTER BIT #
BASE ADDRESS
ENDING ADDRESS
RAM (PD#1)
0x08000000
0x0800FFFF
0(1)
RAM (RAM_PD#1)
0x08010000
0x0801FFFF
0(1)
RAM (RAM_PD#2)
0x08020000
0x0802FFFF
0(1)
RAM (RAM_PD#3)
0x08030000
0x0803FFFF
0(1)
MIBSPI5 RAM
0xFF0A0000
0xFF0BFFFF
12(2)
MIBSPI3 RAM
0xFF0C0000
0xFF0DFFFF
11(2)
MIBSPI1 RAM
0xFF0E0000
0xFF0FFFFF
7(2)
DCAN3 RAM
0xFF1A0000
0xFF1BFFFF
10
DCAN2 RAM
0xFF1C0000
0xFF1DFFFF
6
DCAN1 RAM
0xFF1E0000
0xFF1FFFFF
5
MIBADC2 RAM
0xFF3A0000
0xFF3BFFFF
14
MIBADC1 RAM
0xFF3E0000
0xFF3FFFFF
8
N2HET2 RAM
0xFF440000
0xFF57FFFF
15
N2HET1 RAM
0xFF460000
0xFF47FFFF
3
HTU2 RAM
0xFF4C0000
0xFF4DFFFF
16
HTU1 RAM
0xFF4E0000
0xFF4FFFFF
4
DMA RAM
0xFFF80000
0xFFF80FFF
1
VIM RAM
0xFFF82000
0xFFF82FFF
2
USB Device RAM
RAM is not CPU-Addressable
n/a
Ethernet RAM (CPPI Memory
0xFC520000
0xFC521FFF
n/a
Slave)
(1)
The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized.
(2)
The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset
via the SPIGCR0 register. This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system
module auto-initialization method. Before the MibSPI RAM can be initialized using the system module auto-initialization method: (i) The
module must be released from its local reset, AND (ii) The application must poll for the "BUF INIT ACTIVE" status flag in the SPIFLG
register to become cleared (zero)
Copyright 2012–2013, Texas Instruments Incorporated
System Information and Electrical Specifications
87
Product Folder Links: RM48L950 RM48L750 RM48L550
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