參數(shù)資料
型號: XRM48L950PGET
廠商: Texas Instruments
文件頁數(shù): 13/176頁
文件大?。?/td> 0K
描述: MCU 16/32Bit FLASH 3MB 144LQFP
標(biāo)準(zhǔn)包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 64
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
包裝: 托盤
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
其它名稱: 296-29389
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
2.3
Terminal Functions
Section 2.3.1 and Section 2.3.2 identify the external signal names, the associated pin/ball numbers along
with the mechanical package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether
the pin/ball has any internal pullup/pulldown, whether the pin/ball can be configured as a GPIO, and a
functional pin/ball description. The first signal name listed is the primary function for that terminal. The
signal name in Bold is the function being described. Refer to the RM48x Technical Reference Manual
(SPNU503) for information on how to select between different multiplexed functions.
NOTE
All I/O signals except nRST are configured as inputs while nPORRST is low and immediately
after nPORRST goes High.
All output-only signals are configured as inputs while nPORRST is low, and are configured
as outputs immediately after nPORRST goes High.
While nPORRST is low, the input buffers are disabled, and the output buffers are tri-stated.
In the Terminal Functions table below, the "Default Pull State" is the state of the pullup or
pulldown while nPORRST is low and immediately after nPORRST goes High. The default
pull direction may change when software configures the pin for an alternate function. The
"Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given
terminal.
2.3.1
PGE Package
2.3.1.1
Multi-Buffered Analog-to-Digital Converters (MibADC)
Table 2-1. PGE Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2)
Terminal
Signal
Default
Pull Type
Description
Type
Pull State
Signal Name
144
PGE
ADREFHI(1)
66
Input
-
None
ADC high reference
supply
ADREFLO(1)
67
Input
ADC low reference supply
VCCAD(1)
69
Power
Operating supply for ADC
VSSAD(1)
68
Ground
AD1EVT/MII_RX_ER/RMII_RX_ER
86
I/O
Pull Down
Programmable,
ADC1 event trigger input,
20uA
or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2PIN_nDIS
55
I/O
Pull Up
Programmable,
ADC2 event trigger input,
20uA
or GPIO
AD1IN[0]
60
Input
-
None
ADC1 analog input
AD1IN[1]
71
AD1IN[2]
73
AD1IN[3]
74
AD1IN[4]
76
AD1IN[5]
78
AD1IN[6]
80
AD1IN[7]
61
(1)
The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
Copyright 2012–2013, Texas Instruments Incorporated
Device Package and Terminal Functions
11
Product Folder Links: RM48L950 RM48L750 RM48L550
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