參數(shù)資料
型號： XR17V254IV-0A-EVB
廠商： Exar Corporation
文件頁數(shù)： 9/70頁
文件大小： 0K
描述： EVAL BOARD FOR XR17V254 144LQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR17V254
17
REV. 1.0.1
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
INT3, INT2 and INT1 [32:8]
Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit,
and status. bits [10:8] represent channel 0 and go up to channel 3 with bits [19:17]. Bits [31:20] are reserved.
The 3-bit encoding and their priority order are shown below in Table 8. The Timer and MPIO interrupts are for
the device and therefore they exist within channel 0 space and not in other channel interrupt.
.
FIGURE 5. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3
TABLE 8: UART CHANNEL [3:0] INTERRUPT SOURCE ENCODING
PRIORITY BIT[N+2] BIT[N+1]
BIT[N]
INTERRUPT SOURCE(S)
x
0
None or wake-up indicator
1
0
1
RXRDY and RX Line Status (logic OR of LSR[4:1])
2
0
1
0
RXRDY Time-out
3
0
1
TXRDY, THR or TSR (auto RS485 mode) empty
4
1
0
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
5
1
0
1
Reserved.
6
1
0
MPIO pin(s). Available only within channel 0, reserved in other channels.
7
1
TIMER Time-out. Available only within channel 0, reserved in other channels.
TABLE 9: UART CHANNEL [3:0] INTERRUPT CLEARING
RXRDY and RXRDY Time-out is clear by reading data in the RX FIFO until it falls below the trigger level.
RX Line Status interrupt clears after reading the LSR register that is in the UART channel register set.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon delta and special char detect interrupt clears after reading the ISR register that is in the UART channel reg set.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
Channel-3
Channel-2
Channel-1
Channel-0
INT2 Register
INT1 Register
INT3 Register
INT0 Register
Interrupt Registers,
INT0, INT1, INT2 and INT3
Bit-0
Bit-1
Bit-2
Bit-3
Bit-7
Bit-4
Bit-5
Bit-6
Ch-3 Ch-2 Ch-1 Ch-0
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Rsvd
Rsvd Rsvd
Rsvd
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