參數(shù)資料
型號(hào): XR17V254IV-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 1/70頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR17V254 144LQFP
標(biāo)準(zhǔn)包裝: 1
系列: *
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
JULY 2008
REV. 1.0.1
GENERAL DESCRIPTION
The XR17V2541 (V254) is a single chip 4-channel
66MHz PCI (Peripheral Component Interconnect)
UART
(Universal
Asynchronous
Receiver
and
Transmitter)
solution,
optimized
for
higher
performance and lower power. The V254 device with
its fifth generation register set is designed to meet the
high
bandwidth
and
power
management
requirements for multi-serial communication ports for
system administration and management. The 32-bit
66MHz PCI interface is compliant with PCI 3.0 and
PCI power management revision 1.1 specifications.
The device provides an upgrade path for Exar’s
33MHz 5V and Universal PCI UART family of
products in a 144-pin LQFP package.
The V254 consists of four independent UART
channels,
each
with
set
of
configuration
and
enhanced registers, 64 bytes of Transmit (TX) and
Receive (RX) FIFOs, and a fractional Baud Rate
Generator (BRG). A global interrupt source register
provides a complete interrupt status indication for all
4 channels to speed up interrupt parsing. The V254
device operates at 33/66MHz and features fully
programmable TX and RX FIFO level triggers,
automatic hardware and software flow control, and
automatic RS-485 half duplex direction control output
for software and hardware design simplification.
NOTE 1: Covered by U.S. Patents #5,649,122 and #5,949,787
APPLICATIONS
Remote Access Servers
Storage Network Management
Factory Automation and Process Control
Instrumentation
Multi-port RS-232/RS-422/RS-485 Cards
Point-Of-Sales
FEATURES
High performance 32-bit 66MHz PCI UART
PCI 3.0 compliance
PCI power management rev. 1.1 compliance
EEPROM interface for PCI configuration
3.3V supply with 5V tolerant non-PCI (serial) inputs
Data read/write burst operation
Global interrupt register for all four UART channels
Up to 8 Mbps serial data rate
Eight multi-purpose inputs/outputs
A 16-bit general purpose timer/counter
Sleep mode with wake-up Indicator
Four independent UART channels controlled with
16C550 compatible register Set
64-byte TX and RX FIFOs with level counters
and programmable trigger levels
Fractional baud rate generator
Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
Automatic Xon/Xoff software flow control
RS-485 half duplex direction control output
with selectable turn-around delay
Infrared (IrDA 1.0) data encoder/decoder
FIGURE 1. BLOCK DIAGRAM OF THE XR17V254
TMRCK
Device
Configuration
Registers
XTAL1
XTAL2
Crystal Osc/Buffer
UART Channel 0
TX0, RX0, DTR0#,
DSR0#, RTS0#,
CTS0#, CD0#, RI0#
PCI Local
Bus
Interface
CLK (upto
66MHz)
RST#
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
IDSEL
PERR#
SERR#
Configuration
Space
Registers
.
MPIO0- MPIO7
Multi-purpose
Inputs/Outputs
TX3, RX3, DTR3#,
DSR3#, RTS3#,
CTS3#, CD3#, RI3#
UART Channel 3
UART Channel 2
UART Channel 1
16-bit
Timer/Counter
EECK
EEDI
EEDO
EECS
EEPROM
Interface
64 Byte TX FIFO
64 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
3.3V VCC
(5V Tolerant
Serial Inputs)
INTA#
PME#
GND
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