XR17V254
9
REV. 1.0.1
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
OFFSET
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX OR BINARY)
0x00
31:16
EWR
Device ID (Exar device ID number)
0x0254
15:0
EWR
Vendor ID (Exar) specified by PCISIG
0x13A8
0x04
31
30
29:28
RWC
RO
Parity error detected. Cleared by writing a logic 1.
System error detected. Cleared by writing a logic 1.
Unused
0b
00b
27
RO
Target Abort.
0b
26:25
RO
DEVSEL# timing.
00b
24
RO
Unemployments bus master error reporting bit
0b
23
RO
Fast back to back transactions are supported
1b
22
RO
Reserved Status bit
0b
21
RO
66MHz capable
1b
20
RO
Capabilities List
1b
19:16
RO
Reserved Status bits
0000b
15:9,7,
5,4,3,2
RO
Command bits (reserved)
0x0000
8
RWR
SERR# driver enable. logic 1=enable driver and 0=disable driver
0b
6
RWR
Parity error enable. logic 1=respond to parity error and 0=ignore
0b
1
RWR
Command controls a device’s response to mem space accesses:
0=disable mem space accesses, 1=enable mem space accesses
0b
0
RO
Device’s response to I/O space accesses is disabled.
(0 = disable I/O space accesses)
0b
0x08
31:8
EWR
Class Code (Default is ’Simple 550 Communication Controller’)
0x070002
7:0
RO
Revision ID (Exar device revision number)
Current Rev. value
0x0C
31:24
RO
BIST (Built-in Self Test)
0x00
23:16
RO
Header Type (a single function device with one BAR)
0x00
15:8
RO
Unimplemented Latency Timer (needed only for bus master)
0x00
7:0
RO
Unimplemented Cache Line Size
0x00
0x10
31:11
RWR
Memory Base Address Register (BAR)
0x00
10:0
RO
Claims a 2K address space for the memory mapped UARTs
0x000
0x14
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x18h
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x1C
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x20
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000