參數(shù)資料
型號(hào)： XPC850CZT50BUR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC PROCESSOR, PBGA256
封裝： PLASTIC, BGA-256
文件頁(yè)數(shù)： 9/76頁(yè)
文件大?。?/td> 825K
代理商： XPC850CZT50BUR2
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specications
17
Layout Practices
B31a CLKOUT falling edge to CS valid
- as requested by control bit
CST1 in the corresponding word
in the UPM
5.00
12.00
8.00
14.00
6.00
13.00
0.250
50.00
ns
B31b CLKOUT rising edge to CS valid
- as requested by control bit
CST2 in the corresponding word
in the UPM
1.50
8.00
1.50
8.00
1.50
8.00
—
50.00
ns
B31c
CLKOUT rising edge to CS valid
- as requested by control bit
CST3 in the corresponding word
in the UPM
5.00
12.00
8.00
14.00
6.00
13.00
0.250
50.00
ns
B31d CLKOUT falling edge to CS valid
- as requested by control bit
CST1 in the corresponding word
in the UPM EBDF = 1
9.00
14.00 13.00 18.00 11.00 16.00
0.375
50.00
ns
B32
CLKOUT falling edge to BS valid
- as requested by control bit
BST4 in the corresponding word
in the UPM
1.50
6.00
1.50
6.00
1.50
6.00
—
50.00
ns
B32a CLKOUT falling edge to BS valid
- as requested by control bit
BST1 in the corresponding word
in the UPM, EBDF = 0
5.00
12.00
8.00
14.00
6.00
13.00
0.250
50.00
ns
B32b CLKOUT rising edge to BS valid
- as requested by control bit
BST2 in the corresponding word
in the UPM
1.50
8.00
1.50
8.00
1.50
8.00
—
50.00
ns
B32c
CLKOUT rising edge to BS valid
- as requested by control bit
BST3 in the corresponding word
in the UPM
5.00
12.00
8.00
14.00
6.00
13.00
0.250
50.00
ns
B32d CLKOUT falling edge to BS valid
- as requested by control bit
BST1 in the corresponding word
in the UPM, EBDF = 1
9.00
14.00 13.00 18.00 11.00 16.00
0.375
50.00
ns
B33
CLKOUT falling edge to GPL
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
1.50
6.00
1.50
6.00
1.50
6.00
—
50.00
ns
B33a CLKOUT rising edge to GPL
valid - as requested by control
bit GxT3 in the corresponding
word in the UPM
5.00
12.00
8.00
14.00
6.00
13.00
0.250
50.00
ns
Table 6-6. Bus Operation Timing 1 (continued)
Num
Characteristic
50 MHz
66 MHz
80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min
Max
Min
Max
Min
Max
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