參數(shù)資料
型號(hào): XPC850CZT50BUR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC PROCESSOR, PBGA256
封裝: PLASTIC, BGA-256
文件頁數(shù): 30/76頁
文件大?。?/td> 825K
代理商: XPC850CZT50BUR2
36
MPC850 (Rev. A/B/C) Hardware Specications
MOTOROLA
Layout Practices
Figure 6-24 provides the PCMCIA access cycle timing for the external bus read.
Figure 6-24. PCMCIA Access Cycles Timing External Bus Read
P53
CLKOUT to ALE negate time
13.00
16.00
14.00
0.250
ns
P54
PCWE, IOWR negated to D[0–31]
invalid.1
3.00
6.00
4.00
0.250
ns
P55
WAIT_B valid to CLKOUT rising edge.1
8.00
8.00
8.00
ns
P56
CLKOUT rising edge to WAIT_B invalid.1
2.00
2.00
2.00
ns
1 PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings dene when the WAIT_B signal is detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAIT_B assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.
See PCMCIA Interface in the MPC850 PowerQUICC User’s Manual.
Table 6-8. PCMCIA Timing (continued)
Num
Characteristic
50MHz
66MHz
80 MHz
FFACTOR Unit
Min
Max
Min
Max
Min
Max
CLKOUT
A[6:31]
REG
CE1/CE2
PCOE, IORD
TS
D[0:31]
ALE
B19
B18
P53
P52
P51
P50
P48
P49
P46
P45
P44
P47
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