- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4214 > XCV405E-8FG676C (Xilinx Inc)IC FPGA 1.8V C-TEMP 676-FBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | XCV405E-8FG676C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 66/118頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 676-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 10800 |
| RAM 位總計(jì)： | 573440 |
| 輸入/輸出數(shù)： | 404 |
| 門(mén)數(shù)： | 129600 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)當(dāng)前第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
47
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
GCLKPAD3 can also be replaced with the package pin
name, such as D17 for the BG432 package.
Creating LVDS Input Buffers
An LVDS input buffer can be placed in a wide number of IOB
locations. The exact location is dependent on the package
that is used. The Virtex-E package information lists the pos-
sible locations as IO_L#P for the P-side and IO_L#N for the
N-side where # is the pair number.
HDL Instantiation
Only one input buffer is required to be instantiated in the
design and placed on the correct IO_L#P location. The
N-side of the buffer is reserved and no other IOB is allowed
to be placed on this location. In the physical device, a con-
figuration option is enabled that routes the pad wire from the
IO_L#N IOB to the differential input buffer located in the
IO_L#P IOB. The output of this buffer then drives the output
of the IO_L#P cell or the input register in the IO_L#P IOB. In
EPIC it appears that the second buffer is unused. Any
attempt to use this location for another purpose leads to a
DRC error in the software.
VHDL Instantiation
data0_p : IBUF_LVDS port map (I=>data(0),
O=>data_int(0));
Verilog Instantiation
IBUF_LVDS data0_p (.I(data[0]),
.O(data_int[0]));
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the input buffers this can be done with the following con-
straint in the UCF or NCF file.
NET data<0> LOC = D28; # IO_L0P
Optional N-side
Some designers might prefer to also instantiate the N-side
buffer for the input buffer. This allows the top-level net list to
include net connections for both PCB layout and sys-
tem-level integration. In this case, only the output P-side
IBUF connection has a net connected to it. Since the N-side
IBUF does not have a connection in the EDIF net list, it is
trimmed from the design in MAP.
VHDL Instantiation
data0_p : IBUF_LVDS port map
(I=>data_p(0), O=>data_int(0));
data0_n : IBUF_LVDS port map
(I=>data_n(0), O=>open);
Verilog Instantiation
IBUF_LVDS data0_p (.I(data_p[0]),
.O(data_int[0]));
IBUF_LVDS data0_n (.I(data_n[0]), .O());
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the global clock input buffers this can be done with the fol-
lowing constraint in the UCF or NCF file.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Adding an Input Register
All LVDS buffers can have an input register in the IOB. The
input register is in the P-side IOB only. All the normal IOB
register options are available (FD, FDE, FDC, FDCE, FDP,
FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE,
LDP, LDPE). The register elements can be inferred or
explicitly instantiated in the HDL code.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using “map -pr
[i|o|b]”, where “i” is inputs only, “o” is outputs only, and “b” is
both inputs and outputs.
To improve design coding times VHDL and Verilog synthe-
sis macro libraries available to explicitly create these struc-
tures. The input library macros are listed in Table 42. The I
and IB inputs to the macros are the external net connec-
tions.
Table 42:
Input Library Macros
Name
Inputs
Outputs
IBUFDS_FD_LVDS
I, IB, C
Q
IBUFDS_FDE_LVDS
I, IB, CE, C
Q
IBUFDS_FDC_LVDS
I, IB, C, CLR
Q
IBUFDS_FDCE_LVDS
I, IB, CE, C, CLR
Q
IBUFDS_FDP_LVDS
I, IB, C, PRE
Q
IBUFDS_FDPE_LVDS
I, IB, CE, C, PRE
Q
IBUFDS_FDR_LVDS
I, IB, C, R
Q
IBUFDS_FDRE_LVDS
I, IB, CE, C, R
Q
IBUFDS_FDS_LVDS
I, IB, C, S
Q
IBUFDS_FDSE_LVDS
I, IB, CE, C, S
Q
IBUFDS_LD_LVDS
I, IB, G
Q
IBUFDS_LDE_LVDS
I, IB, GE, G
Q
IBUFDS_LDC_LVDS
I, IB, G, CLR
Q
IBUFDS_LDCE_LVDS
I, IB, GE, G, CLR
Q
IBUFDS_LDP_LVDS
I, IB, G, PRE
Q
IBUFDS_LDPE_LVDS
I, IB, GE, G, PRE
Q
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV405E-7FG676I | IC FPGA 1.8V 676-BGA |
| XC6VLX195T-1FFG784C | IC FPGA VIRTEX 6 199K 784FFGBGA |
| XC6VCX130T-2FFG784I | IC FPGA VIRTEX 6 128K 784FFGBGA |
| XC4VLX60-11FF668I | IC FPGA VIRTEX-4LX 668FFBGA |
| XC4VLX60-12FFG668C | IC FPGA VIRTEX-4 LX 60K 668FCBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV405E-8FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV50 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV50-4BG256C | 功能描述:IC FPGA 2.5V C-TEMP 256-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。