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參數(shù)資料
| 型號(hào)： | XCV405E-8FG676C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 31/118頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 676-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 10800 |
| RAM 位總計(jì)： | 573440 |
| 輸入/輸出數(shù)： | 404 |
| 門數(shù)： | 129600 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
R
Module 1 of 4
DS025-1 (v3.0) March 21, 2014
2
Production Product Specification
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Virtex-E Compared to Virtex Devices
The Virtex-E family offers up to 43,200 logic cells in devices
up to 30% faster than the Virtex family.
I/O performance is increased to 622 Mb/s using Source
Synchronous data transmission architectures and synchro-
nous system performance up to 240 MHz using sin-
gled-ended SelectI/O technology. Additional I/O standards
are supported, notably LVPECL, LVDS, and BLVDS, which
use two pins per signal. Almost all signal pins can be used
for these new standards.
Virtex-E devices have up to 640 Kb of faster (250MHz)
block SelectRAM, but the individual RAMs are the same
size and structure as in the Virtex family. They also have
eight DLLs instead of the four in Virtex devices. Each indi-
vidual DLL is slightly improved with easier clock mirroring
and 4x frequency multiplication.
VCCINT, the supply voltage for the internal logic and mem-
ory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced
processing and 0.18
μm design rules have resulted in
smaller dice, faster speed, and lower power consumption.
I/O pins are 3 V tolerant, and can be 5 V tolerant with an
external 100
Ω resistor. PCI 5 V is not supported. With the
addition of appropriate external resistors, any pin can toler-
ate any voltage desired.
Banking rules are different. With Virtex devices, all input
buffers are powered by VCCINT. With Virtex-E devices, the
LVTTL, LVCMOS2, and PCI input buffers are powered by
the I/O supply voltage VCCO.
The Virtex-E family is not bitstream-compatible with the Vir-
tex family, but Virtex designs can be compiled into equiva-
lent Virtex-E devices.
The same device in the same package for the Virtex-E and
Virtex families are pin-compatible with some minor excep-
tions. See the data sheet pinout section for details.
General Description
The Virtex-E FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 6-layer metal 0.18
μm CMOS process. These
advances make Virtex-E FPGAs powerful and flexible alter-
natives to mask-programmed gate arrays. The Virtex-E fam-
ily includes the nine members in Table 1.
Building on experience gained from Virtex FPGAs, the Vir-
tex-E family is an evolutionary step forward in programma-
ble logic design. Combining a wide variety of programmable
system features, a rich hierarchy of fast, flexible intercon-
nect resources, and advanced process technology, the Vir-
programmable logic solution that enhances design flexibility
while reducing time-to-market.
Virtex-E Architecture
Virtex-E devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the
Virtex-E family to accommodate even the largest and most
complex designs.
Virtex-E FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. Con-
figuration data can be read from an external SPROM (mas-
ter serial mode), or can be written into the FPGA
(SelectMAP, slave serial, and JTAG modes).
The standard Xilinx Foundation Series and Alliance
Series Development systems deliver complete design
support for Virtex-E, covering every aspect from behavioral
and schematic entry, through simulation, automatic design
translation and implementation, to the creation and down-
loading of a configuration bit stream.
Higher Performance
Virtex-E devices provide better performance than previous
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architech-
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-
tions, and interfaces can be implemented that operate at
33 MHz or 66 MHz.
While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can
achieve over 311 MHz. Table 2, page 3, shows perfor-
mance data for representative circuits, using worst-case
timing parameters.
Table 1: Virtex-E Extended Memory Field-Programmable Gate Array Family Members
Device
Logic Gates
CLB Array
Logic
Cells
Differential
I/O Pairs
User I/O
BlockRAM
Bits
Distributed
RAM Bits
XCV405E
129,600
40 x 60
10,800
183
404
573,440
153,600
XCV812E
254,016
56 x 84
21,168
201
556
1,146,880
301,056
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV405E-8FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV50 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV50-4BG256C | 功能描述:IC FPGA 2.5V C-TEMP 256-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
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