參數資料
型號: XCV405E-8FG676C
廠商: Xilinx Inc
文件頁數: 60/118頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V C-TEMP 676-FBGA
產品變化通告: FPGA Family Discontinuation 18/Apr/2011
標準包裝: 1
系列: Virtex®-E EM
LAB/CLB數: 2400
邏輯元件/單元數: 10800
RAM 位總計: 573440
輸入/輸出數: 404
門數: 129600
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 676-BGA
供應商設備封裝: 676-FBGA(27x27)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
42
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
SSTL3_I
A sample circuit illustrating a valid termination technique for
SSTL3_I appears in Figure 49. DC voltage specifications
appear in Table 28.
SSTL3_II
A sample circuit illustrating a valid termination technique for
SSTL3_II appears in Figure 50. DC voltage specifications
appear in Table 29.
SSTL2_I
A sample circuit illustrating a valid termination technique for
SSTL2_I appears in Figure 51. DC voltage specifications
appear in Table 30.
Figure 49: Terminated SSTL3 Class I
Table 28:
SSTL3_I Voltage Specifications
Parameter
Min
Typ
Max
VCCO
3.0
3.3
3.6
VREF = 0.45 × VCCO
1.3
1.5
1.7
VTT = VREF
1.3
1.5
1.7
VIH = VREF + 0.2
1.5
1.7
3.9(1)
VIL = VREF – 0.2
0.3(2)
1.3
1.5
VOH = VREF + 0.6
1.9
-
VOL = VREF – 0.6
-
1.1
IOH at VOH (mA)
8-
-
IOLat VOL (mA)
8
-
Notes:
1.
VIH maximum is VCCO + 0.3
2.
VIL minimum does not conform to the formula
Figure 50: Terminated SSTL3 Class II
50
Ω
Z = 50
SSTL3 Class I
x133_13_111699
25
Ω
VREF = 1.5V
VTT= 1.5V
VCCO = 3.3V
50
Ω
Z = 50
SSTL3 Class II
x133_14_111699
25
Ω
50
Ω
VREF = 1.5V
VTT= 1.5V
VCCO = 3.3V
Table 29:
SSTL3_II Voltage Specifications
Parameter
Min
Typ
Max
VCCO
3.0
3.3
3.6
VREF = 0.45 × VCCO
1.3
1.5
1.7
VTT = VREF
1.3
1.5
1.7
VIH = VREF + 0.2
1.5
1.7
3.9(1)
VIL= VREF – 0.2
0.3(2)
1.3
1.5
VOH = VREF + 0.8
2.1
-
VOL= VREF – 0.8
-
0.9
IOH at VOH (mA)
16
-
IOLat VOL (mA)
16
-
Notes:
1.
VIH maximum is VCCO + 0.3
2.
VIL minimum does not conform to the formula
Figure 51: Terminated SSTL2 Class I
Table 30:
SSTL2_I Voltage Specifications
Parameter
Min
Typ
Max
VCCO
2.3
2.5
2.7
VREF = 0.5 × VCCO
1.15
1.25
1.35
VTT = VREF + N(1)
1.11
1.25
1.39
VIH = VREF + 0.18
1.33
1.43
3.0(2)
VIL = VREF – 0.18
0.3(3)
1.07
1.17
VOH = VREF + 0.61
1.76
-
VOL= VREF – 0.61
-
0.74
IOH at VOH (mA)
7.6
-
IOLat VOL (mA)
7.6
-
Notes:
1.
N must be greater than or equal to –0.04 and less than or
equal to 0.04.
2.
VIH maximum is VCCO + 0.3.
3.
VIL minimum does not conform to the formula.
50
Ω
Z = 50
SSTL2 Class I
xap133_15_011000
25
Ω
V
REF
= 1.25V
V
TT
= 1.25V
V
CCO
= 2.5V
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XCV50-4BG256C 功能描述:IC FPGA 2.5V C-TEMP 256-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現場可編程門陣列) 系列:Virtex® 標準包裝:1 系列:Kintex-7 LAB/CLB數:25475 邏輯元件/單元數:326080 RAM 位總計:16404480 輸入/輸出數:350 門數:- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,FCBGA 供應商設備封裝:900-FCBGA(31x31) 其它名稱:122-1789