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參數(shù)資料
| 型號(hào)： | XCV3200E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex-E 1.8 V Field Programmable Gate Arrays(Virtex-E 1.8V 現(xiàn)場可編程門陣列) |
| 中文描述： | 的Virtex娥1.8伏現(xiàn)場可編程門陣列（的Virtex娥1.8V的現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 9/220頁 |
| 文件大小： | 1838K |
| 代理商： | XCV3200E |
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General Purpose Routing
Most Virtex-E signals are routed on the general purpose
routing, and consequently, the majority of interconnect
resources are associated with this level of the routing hier-
archy. General-purpose routing resources are located in
horizontal and vertical routing channels associated with the
CLB rows and columns and are as follows:
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
72 buffered Hex lines route GRM signals to another
GRMs six-blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
are driven only at their endpoints. Hex-line signals can
be accessed either at the endpoints or at the midpoint
(three blocks from the source). One third of the Hex
lines are bidirectional, while the remaining ones are
uni-directional.
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
I/O Routing
Virtex-E devices have additional routing resources around
their periphery that form an interface between the CLB array
and the IOBs. This additional routing, called the
VersaRing, facilitates pin-swapping and pin-locking, such
that logic redesigns can adapt to existing PCB layouts.
Time-to-market is reduced, since PCBs and other system
components can be manufactured while the logic design is
still in progress.
Dedicated Routing
Some classes of signal require dedicated routing resources to
maximize performance. In the Virtex-E architecture, dedi-
cated routing resources are provided for two classes of signal.
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in
Figure 8
.
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.Global Clock Distribution
Network
DLL Location
Clock Routing
Clock Routing resources distribute clocks and other signals
with very high fanout throughout the device. Virtex-E
devices include two tiers of clock routing resources referred
to as global and local clock routing resources.
The global routing resources are four dedicated global
nets with dedicated input pins that are designed to
distribute high-fanout clock signals with minimal skew.
Each global clock net can drive all CLB, IOB, and block
RAM clock pins. The global nets can be driven only by
global buffers. There are four global buffers, one for
each global net.
The local clock routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These local resources are
more flexible than the global resources since they are
not restricted to routing only to clock pins.
Figure 7:
Virtex-E Local Routing
XCVE_ds_007
CLB
GRM
To
Adjacent
GRM
To Adjacent
GRM
Direct
To Adjacent
GRM
To Adjacent
GRM
DirectTo Adjacent
CLB
Figure 8:
BUFT Connections to Dedicated Horizontal Bus LInes
CLB
CLB
CLB
CLB
buft_c.eps
Tri-State
Lines
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PDF描述 |
|---|---|
| XCV600E | Virtex-E 1.8 V Field Programmable Gate Arrays(Virtex-E 1.8V 現(xiàn)場可編程門陣列) |
| XCV405E | Extended Memory Field Programmable Gate Arrays |
| XCV405E-6BG560C | Extended Memory Field Programmable Gate Arrays |
| XCV405E-6BG560I | Extended Memory Field Programmable Gate Arrays |
| XCV405E-6FG560C | Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV3200E-6BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV3200E-6BG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex?-E 1.8 V Field Programmable Gate Arrays |
| XCV3200E-6CG1156C | 功能描述:IC FPGA 1.8V C-TEMP 1156-CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV3200E-6FG1156C | 制造商:Xilinx 功能描述: |
| XCV3200E-6FG1156I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
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