參數(shù)資料
型號(hào)： XCV3200E
廠商： Xilinx, Inc.
英文描述： Virtex-E 1.8 V Field Programmable Gate Arrays(Virtex-E 1.8V 現(xiàn)場(chǎng)可編程門陣列)
中文描述： 的Virtex娥1.8伏現(xiàn)場(chǎng)可編程門陣列（的Virtex娥1.8V的現(xiàn)場(chǎng)可編程門陣列）
文件頁(yè)數(shù)： 3/220頁(yè)
文件大?。?/td> 1838K
代理商： XCV3200E
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Virtex
-E 1.8 V Field Programmable Gate Arrays
DS022 (v1.9) February 12, 2001
1-800-255-7778
3
R
interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the
Virtex-E family to accommodate even the largest and most
complex designs.
Virtex-E FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. Con-
figuration data can be read from an external SPROM (mas-
ter serial mode), or can be written into the FPGA
(SelectMAP
, slave serial, and JTAG modes).
The standard Xilinx Foundation Series
and Alliance
Series
Development systems deliver complete design
support for Virtex-E, covering every aspect from behavioral
and schematic entry, through simulation, automatic design
translation and implementation, to the creation and down-
loading of a configuration bit stream.
Higher Performance
Virtex-E devices provide better performance than previous
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architech-
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-
tions, and interfaces can be implemented that operate at
33 MHz or 66 MHz.
While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can
achieve over 311 MHz.
Table 2
shows performance data for
representative circuits, using worst-case timing parameters.
Architectural Description
Virtex-E Array
The Virtex-E user-programmable gate array, shown in
Figure 1
, comprises two major configurable elements: con-
figurable logic blocks (CLBs) and input/output blocks
(IOBs).
CLBs provide the functional elements for constructing
logic
IOBs provide the interface between the package pins
and the CLBs
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock
that also provides local
routing resources to connect the CLB to the GRM.
The VersaRing
I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
The Virtex-E architecture also includes the following circuits
that connect to the GRM.
Dedicated block memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
3-State buffers (BUFTs) associated with each CLB that
drive
dedicated
segmentable
resources
horizontal
routing
Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.
Table 2:
Performance for Common Circuit Functions
Function
Bits
Virtex-E (-7)
Register-to-Register
Adder
16
64
4.3 ns
6.3 ns
Pipelined Multiplier
8 x 8
16 x 16
4.4 ns
5.1 ns
Address Decoder
16
64
3.8 ns
5.5 ns
16:1 Multiplexer
4.6 ns
Parity Tree
9
18
36
3.5 ns
4.3 ns
5.9 ns
Chip-to-Chip
HSTL Class IV
LVTTL,16mA, fast slew
LVDS
LVPECL
Figure 1:
Virtex-E Architecture Overview
DLLDLL
I
I
VersaRing
VersaRing
ds022_01_121099
C
B
B
B
C
C
B
C
DLLDLL
DLLDLL
DLLDLL
相關(guān)PDF資料
PDF描述
XCV600E Virtex-E 1.8 V Field Programmable Gate Arrays(Virtex-E 1.8V 現(xiàn)場(chǎng)可編程門陣列)
XCV405E Extended Memory Field Programmable Gate Arrays
XCV405E-6BG560C Extended Memory Field Programmable Gate Arrays
XCV405E-6BG560I Extended Memory Field Programmable Gate Arrays
XCV405E-6FG560C Extended Memory Field Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV3200E-6BG240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays
XCV3200E-6BG240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex?-E 1.8 V Field Programmable Gate Arrays
XCV3200E-6CG1156C 功能描述:IC FPGA 1.8V C-TEMP 1156-CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-E 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
XCV3200E-6FG1156C 制造商:Xilinx 功能描述:
XCV3200E-6FG1156I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays
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