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參數(shù)資料
| 型號(hào)： | XCV3200E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex-E 1.8 V Field Programmable Gate Arrays(Virtex-E 1.8V 現(xiàn)場可編程門陣列) |
| 中文描述： | 的Virtex娥1.8伏現(xiàn)場可編程門陣列（的Virtex娥1.8V的現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 5/220頁 |
| 文件大?。?/td> | 1838K |
| 代理商： | XCV3200E |
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buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients.
In most signalling standards, the output High voltage
depends on an externally supplied V
CCO
voltage. The need
to supply V
CCO
imposes constraints on which standards
can be used in close proximity to each other.
See "I/O Bank-
ing" on page 5.
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
Since the weak-keeper circuit uses the IOB input buffer to
monitor the input level, an appropriate V
REF
voltage must be
provided if the signalling standard requires one. The provi-
sion of this voltage must comply with the I/O banking rules.
I/O Banking
Some of the I/O standards described above require V
CCO
and/or V
REF
voltages. These voltages are externally sup-
plied and connected to device pins that serve groups of
IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in
Figure 3
. Each bank has
multiple V
CCO
pins, all of which must be connected to the
same voltage. This voltage is determined by the output
standards in use.
Within a bank, output standards can be mixed only if they
use the same V
CCO
. Compatible standards are shown in
Table 4
. GTL and GTL+ appear under all voltages because
their open-drain outputs do not depend on V
CCO
.
Some input standards require a user-supplied threshold
voltage, V
REF
. In this case, certain user-I/O pins are auto-
matically configured as inputs for the V
REF
voltage. Approx-
imately one in six of the I/O pins in the bank assume this
role.
The V
REF
pins within a bank are interconnected internally
and consequently only one V
REF
voltage can be used within
each bank. All V
REF
pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
Within a bank, inputs that require V
REF
can be mixed with
those that do not. However, only one V
REF
voltage can be
used within a bank.
In Virtex-E, input buffers with LVTTL, LVCMOS2,
LVCMOS18, PCI33_3, PCI66_3 standards are supplied by
V
CCO
rather than V
CCINT
. For these standards, only input
and output buffers that have the same V
CCO
can be mixed
together.
The V
CCO
and V
REF
pins for each bank appear in the device
pin-out tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
Within a given package, the number of V
REF
and V
CCO
pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to V
REF
pins. Since these are always
a super set of the V
REF
pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device if necessary. All the V
REF
pins for the largest device
anticipated must be connected to the V
REF
voltage, and not
used for I/O.
In smaller devices, some V
CCO
pins used in larger devices
do not connect within the package. These unconnected pins
can be left unconnected externally, or can be connected to
the V
CCO
voltage to permit migration to a larger device if
necessary.
Figure 3:
Virtex-E I/O Banks
ds022_03_121799
Bank 0
GCLK3 GCLK2
GCLK1 GCLK0
Bank 1
Bank 5
Bank 4
VirtexE
Device
B
B
B
B
Table 4:
Compatible Output Standards
V
CCO
Compatible Standards
3.3 V
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
GTL+, LVPECL
2.5 V
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,
BLVDS, LVDS
1.8 V
LVCMOS18, GTL, GTL+
1.5 V
HSTL I, HSTL III, HSTL IV, GTL, GTL+
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV600E | Virtex-E 1.8 V Field Programmable Gate Arrays(Virtex-E 1.8V 現(xiàn)場可編程門陣列) |
| XCV405E | Extended Memory Field Programmable Gate Arrays |
| XCV405E-6BG560C | Extended Memory Field Programmable Gate Arrays |
| XCV405E-6BG560I | Extended Memory Field Programmable Gate Arrays |
| XCV405E-6FG560C | Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV3200E-6BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV3200E-6BG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex?-E 1.8 V Field Programmable Gate Arrays |
| XCV3200E-6CG1156C | 功能描述:IC FPGA 1.8V C-TEMP 1156-CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV3200E-6FG1156C | 制造商:Xilinx 功能描述: |
| XCV3200E-6FG1156I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
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