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參數(shù)資料
| 型號： | XC9536XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | FastFLASH High-Performance CPLD(FastFLASH 高性能復(fù)雜可編程邏輯器件) |
| 中文描述： | FastFLASH高性能的CPLD（FastFLASH高性能復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 143K |
| 代理商： | XC9536XL |
R
June 7, 1999 (Version 1.5)
5-17
FastFLASH XC9500XL High-Performance CPLD Family
5
unauthorized reading or inadvertent device erasure/repro-
gramming.
Table 3
shows the four different security set-
tings available.
The read security bits can be set by the user to prevent the
internal programming pattern from being read or copied.
When set, they also inhibit further program operations but
allow device erase. Erasing the entire device is the only
way to reset the read security bit.
The write security bits provide added protection against
accidental device erasure or reprogramming when the
JTAG pins are subject to noise, such as during system
power-up. Once set, the write-protection may be deacti-
vated when the device needs to be reprogrammed with a
valid pattern with a specific sequence of JTAG instructions.
Table 3: Data Security Options
Low Power Mode
All XC9500XL devices offer a low-power mode for individ-
ual macrocells or across all macrocells. This feature allows
the device power to be significantly reduced.
Each individual macrocell may be programmed in
low-power mode by the user. Performance-critical parts of
the application can remain in standard power mode, while
other parts of the application may be programmed for
low-power operation to reduce the overall power dissipa-
tion. Macrocells programmed for low-power mode incur
additional delay (t
LP
) in pin-to-pin combinatorial delay as
well as register setup time. Product term clock to output
and product term output enable delays are unaffected by
the macrocell power-setting.
Timing Model
The uniformity of the XC9500XL architecture allows a sim-
plified timing model for the entire device. The basic timing
model, shown in
Figure 15
, is valid for macrocell functions
that use the direct product terms only, with standard power
setting, and standard slew rate setting.
Table 4
shows how
each of the key timing parameters is affected by the prod-
uct term allocator (if needed), low-power setting, and
slew-limited setting.
The product term allocation time depends on the logic span
of the macrocell function, which is defined as one less than
the maximum number of allocators in the product term
path. If only direct product terms are used, then the logic
span is 0. The example in
Figure 6
shows that up to 15
product terms are available with a span of 1. In the case of
Figure 7
, the 18 product term function has a span of 2.
Read Allowed
Program/Erase
Allowed
Read Inhibited
Program Inhibit
Erase Allowed
Read Allowed
Program/Erase
Allowed
Read Inhibited
Program/Erase
Inhibited
Read Security
Default
Set
Default
Set
W
X5902
GND
V
CC
(a)
(b)
Figure 14: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
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