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參數(shù)資料
| 型號(hào)： | XC9536XL |
| 廠(chǎng)商： | Xilinx, Inc. |
| 英文描述： | FastFLASH High-Performance CPLD(FastFLASH 高性能復(fù)雜可編程邏輯器件) |
| 中文描述： | FastFLASH高性能的CPLD（FastFLASH高性能復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 143K |
| 代理商： | XC9536XL |
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FastFLASH XC9500XL High-Performance CPLD Family
5-16
June 7, 1999 (Version 1.5)
routing switches in the FastCONNECT II switch matrix, a
54-wide input Function Block, and flexible, bi-directional
product term allocation within each macrocell. These fea-
tures address design changes that require adding or
changing internal routing, including additional signals into
existing equations, or increasing equation complexity,
respectively.
For extensive design changes requiring higher logic capac-
ity than is available in the initially chosen device, the new
design may be able to fit into a larger pin-compatible device
using the same pin assignments. The same board may be
used with a higher density device without the expense of
board rework.
In-System Programming
One or more XC9500XL devices can be daisy chained
together and programmed in-system via a standard 4-pin
JTAG protocol, as shown in
Figure 14
. In-system program-
ming offers quick and efficient design iterations and elimi-
nates package handling. The Xilinx development system
provides the programming data sequence using a Xilinx
download cable, a third-party JTAG development system,
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence.
All I/Os are 3-stated and pulled high by the bus-hold cir-
cuitry during in-system programming. If a particular signal
must remain low during this time, then a pulldown resistor
may be added to the pin.
External Programming
XC9500XL devices can also be programmed by the Xilinx
HW-130 device programmer as well as third-party pro-
grammers. This provides the added flexibility of using
pre-programmed devices during manufacturing, with an
in-system programmable option for future enhancements
and design changes.
Reliability and Endurance
All XC9500XL CPLDs provide a minimum endurance level
of 10,000 in-system program/erase cycles and a minimum
data retention of 20 years. Each device meets all func-
tional, performance, and data retention specifications
within this endurance limit.
IEEE 1149.1 Boundary-Scan (JTAG)
XC9500XL devices fully support IEEE 1149.1 bound-
ary-scan (JTAG). EXTEST, SAMPLE/PRELOAD, BYPASS,
USERCODE, INTEST, IDCODE, HIGHZ and CLAMP
instructions are supported in each device. Additional
instructions are included for in-system programming opera-
tions.
Design Security
XC9500XL devices incorporate advanced data security
features which fully protect the programming data against
Time
0
0
1.5 V
Standard
Output
Voltage
(a)
Slew-Rate Limited
t
SLEW
Time
1.5 V
Output
Voltage
(b)
t
SLEW
Standard
Slew-Rate Limited
X5900_01
V
V
CCIO
Figure 12: Output Slew-Rate Control For (a) Rising and (b) Falling Outputs
I/O
R
BH
Drive to
V
V
CCIO
level
Set to PIN
during valid user
operation
PIN
0
99011200
Figure 13: Bus-Hold Logic
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| XC9536XL-10VQ44C | T1/E1 Transformer |
| XC9536-10VQ44I | XC9536 In-System Programmable CPLD |
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| XC9536XL-10CS48I | 功能描述:IC CPLD 36 MCELL I-TEMP 48-CSP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500XL 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類(lèi)型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門(mén)數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤(pán) |
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